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Richard M. Chou: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ning Jiang, Richard M. Chou, Kewal K. Saluja
    Synthesizing Finite State Machines for Minimum Length Synchronizing Sequence Using Partial Scan. [Citation Graph (0, 0)][DBLP]
    FTCS, 1995, pp:41-49 [Conf]
  2. Richard M. Chou, Kewal K. Saluja
    Sequential Circuit Testing: From DFT to SFT. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1997, pp:274-278 [Conf]
  3. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Power Constraint Scheduling of Tests. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1994, pp:271-274 [Conf]
  4. Richard M. Chou, Kewal K. Saluja
    Testable Sequential Circuit Design: A Partition and Resynthesis Approach. [Citation Graph (0, 0)][DBLP]
    VTS, 2001, pp:62-67 [Conf]
  5. Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal
    Scheduling tests for VLSI systems under power constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:175-185 [Journal]

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