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D. L. Tao: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]
Publications of Author
- Kamal Kantawala, D. L. Tao
Designing Concurrent Checking Sorting Networks. [Citation Graph (0, 0)][DBLP]
FTCS, 1993, pp:250-259 [Conf] - D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A Concurrent Testing Strategy for PLAs. [Citation Graph (0, 0)][DBLP]
ITC, 1986, pp:705-709 [Conf] - D. L. Tao
Evaluating Reliability Improvements of Fault Tolerant VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP]
SPDP, 1992, pp:140-147 [Conf] - N. W. Lo, Bradley S. Carlson, D. L. Tao
Fault Tolerant Algorithms for Broadcasting on the Star Graph Network. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1997, v:46, n:12, pp:1357-1362 [Journal] - D. L. Tao
A Self-Testing Nonincreasing Order Checker. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1997, v:46, n:7, pp:817-820 [Journal] - D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A Note on t-EC/d-UED Codes. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1991, v:40, n:5, pp:660-663 [Journal] - D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1992, v:41, n:7, pp:881-886 [Journal] - D. L. Tao, Kamal Kantawala
Evaluating Reliability Improvements of Fault Tolerant Array Processors Using Algorithm-Based Fault Tolerance. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Computers, 1997, v:46, n:6, pp:725-730 [Journal] - D. L. Tao, Carlos R. P. Hartmann
A Novel Concurrent Error Detection Scheme for FFT Networks. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 1993, v:4, n:2, pp:198-221 [Journal] - D. L. Tao, Carlos R. P. Hartmann, Yunghsing S. (Sam) Han
New Encoding/Decoding Methods for Designing Fault-Tolerant Matrix Operations. [Citation Graph (0, 0)][DBLP]
IEEE Trans. Parallel Distrib. Syst., 1996, v:7, n:9, pp:931-938 [Journal] - Kamal Kantawala, D. L. Tao
Design, analysis, and evaluation of concurrent checking sorting networks. [Citation Graph (0, 0)][DBLP]
IEEE Trans. VLSI Syst., 1997, v:5, n:3, pp:338-343 [Journal]
A new algorithm-based fault tolerance technique for computing matrix operations. [Citation Graph (, )][DBLP]
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