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Atsushi Iwata: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Kan'ya Sasaki, Seiji Kameda, Atsushi Iwata
    Stereo Matching Algorithm Using a Weighted Average of Costs Aggregated by Various Window Sizes. [Citation Graph (0, 0)][DBLP]
    ACCV (2), 2006, pp:771-780 [Conf]
  2. Kenichi Murakoshi, Takashi Morie, Makoto Nagata, Atsushi Iwata
    An arbitrary chaos generator core curcuit using PWM/PPM signals. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:23-24 [Conf]
  3. Makoto Nagata, Atsushi Iwata
    Substrate crosstalk analysis in mixed signal CMOS integrated circuits: embedded tutorial. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:623-630 [Conf]
  4. Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka
    Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2002, pp:71-76 [Conf]
  5. Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata
    Test circuits for substrate noise evaluation in CMOS digital ICs. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2001, pp:13-14 [Conf]
  6. Noriaki Takeda, Mitsuru Homma, Makoto Nagata, Takashi Morie, Atsushi Iwata
    A smart imager for the vision processing front-END. [Citation Graph (0, 0)][DBLP]
    ASP-DAC, 2000, pp:19-20 [Conf]
  7. Osamu Nomura, Takashi Morie, Masakazu Matsugu, Atsushi Iwata
    A Convolutional Neural Network VLSI Architecture Using Sorting Model for Reducing Multiply-and-Accumulation Operations. [Citation Graph (0, 0)][DBLP]
    ICNC (3), 2005, pp:1006-1014 [Conf]
  8. Hiroshi Ando, Takashi Morie, Makoto Nagata, Atsushi Iwata
    Oscillator Networks for Image Segmentation and Their Circuits Using Pulse Modulation Method. [Citation Graph (0, 0)][DBLP]
    ICONIP, 1998, pp:586-589 [Conf]
  9. Souta Sakabayashi, Takashi Morie, Makoto Nagata, Atsushi Iwata
    Nonlinear Function Generators and Chaotic Signal Generators Based on Pulse-Phase Modulation. [Citation Graph (0, 0)][DBLP]
    ICONIP, 1998, pp:582-585 [Conf]
  10. Atsushi Iwata, Makoto Nagata, Hiroyuki Nakamoto, Noriaki Takeda, Mitsuru Homma, Hiroto Higashi, Takashi Morie
    A Feature Associative Processor for Image Recognition Based on A-D merged Architecture. [Citation Graph (0, 0)][DBLP]
    VLSI, 1999, pp:77-88 [Conf]
  11. Takeshi Yoshida, Miho Akagi, Mamoru Sasaki, Atsushi Iwata
    A 1V supply successive approximation ADC with rail-to-rail input voltage range. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:192-195 [Conf]
  12. Yoshitaka Murasaka, Makoto Nagata, Takafumi Ohmoto, Takashi Morie, Atsushi Iwata
    Chip-Level Substrate Noise Analysis with Network Reduction by Fundamental Matrix Computation. [Citation Graph (0, 0)][DBLP]
    ISQED, 2001, pp:482-487 [Conf]
  13. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
    A Convolutional Neural Network VLSI for Image Recognition Using Merged/Mixed Analog-Digital Architecture. [Citation Graph (0, 0)][DBLP]
    KES, 2003, pp:169-176 [Conf]
  14. Osamu Nomura, Takashi Morie, Keisuke Korekado, Masakazu Matsugu, Atsushi Iwata
    A Convolutional Neural Network VLSI Architecture Using Thresholding and Weight Decomposition. [Citation Graph (0, 0)][DBLP]
    KES, 2004, pp:995-1001 [Conf]
  15. Takashi Morie, Tomohiro Matsuura, Makoto Nagata, Atsushi Iwata
    An Efficient Clustering Algorithm Using Stochastic Association Model and Its Implementation Using Nanostructures. [Citation Graph (0, 0)][DBLP]
    NIPS, 2001, pp:1115-1122 [Conf]
  16. Makoto Nagata, Yoshitaka Murasaka, Youichi Nishimori, Takashi Morie, Atsushi Iwata
    Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2002, pp:71-76 [Conf]
  17. Atsushi Iwata, N. Mori, Chinatsu Ikeda, Hiroshi Suzuki, Maximilian Ott
    ATM Connection and Traffic Management Schemes for Multimedia Internetworking. [Citation Graph (0, 0)][DBLP]
    Commun. ACM, 1995, v:38, n:2, pp:72-89 [Journal]
  18. Norihito Fujita, Yuichi Ishikawa, Atsushi Iwata, Rauf Izmailov
    Coarse-grain replica management strategies for dynamic replication of Web contents. [Citation Graph (0, 0)][DBLP]
    Computer Networks, 2004, v:45, n:1, pp:19-34 [Journal]
  19. Rauf Izmailov, Atsushi Iwata, Bhaskar Sengupta
    ATM Routing Algorithms for Multimedia Traffic in Private ATM Networks. [Citation Graph (0, 0)][DBLP]
    J. Heuristics, 2000, v:6, n:1, pp:21-38 [Journal]
  20. Tsutomu Yoshimura, Atsushi Iwata
    An analysis of interference in synchronous systems. [Citation Graph (0, 0)][DBLP]
    IEICE Electronic Express, 2004, v:1, n:15, pp:465-471 [Journal]
  21. Keisuke Korekado, Takashi Morie, Osamu Nomura, Hiroshi Ando, Teppei Nakano, Masakazu Matsugu, Atsushi Iwata
    A VLSI convolutional neural network for image recognition using merged/mixed analog-digital architecture. [Citation Graph (0, 0)][DBLP]
    Journal of Intelligent and Fuzzy Systems, 2004, v:15, n:3-4, pp:173-179 [Journal]
  22. Makoto Nagata, Jin Nagai, Takashi Morie, Atsushi Iwata
    Measurements and analyses of substrate noise waveform inmixed-signal IC environment. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2000, v:19, n:6, pp:671-678 [Journal]
  23. Nobuharu Kami, Jun Suzuki, Yoichi Hidaka, Takashi Yoshikawa, Atsushi Iwata
    Multilayer In-service Reconfiguration for Network Computing Systems. [Citation Graph (0, 0)][DBLP]
    NCA, 2007, pp:324-331 [Conf]

  24. High-Speed, Short-Latency Multipath Ethernet Transport for Interconnections. [Citation Graph (, )][DBLP]


  25. Off-the-path flow handling mechanism forhigh-speed and programmable traffic management. [Citation Graph (, )][DBLP]


  26. High-Speed, Short-Latency Multipath Ethernet for Data Center Area Communications. [Citation Graph (, )][DBLP]


  27. A cellular-automaton-type image extraction algorithm and its implementation using an FPGA. [Citation Graph (, )][DBLP]


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