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Abdelmajid Bouajila:
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- Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
An Architecture for Runtime Evaluation of SoC Reliability. [Citation Graph (0, 0)][DBLP] GI Jahrestagung (1), 2006, pp:177-0 [Conf]
- Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
Organic Computing at the System on Chip Level. [Citation Graph (0, 0)][DBLP] VLSI-SoC, 2006, pp:338-341 [Conf]
A rapid prototyping system for error-resilient multi-processor systems-on-chip. [Citation Graph (, )][DBLP]
Learning Classifier Tables for Autonomic Systems on Chip. [Citation Graph (, )][DBLP]
Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. [Citation Graph (, )][DBLP]
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