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Charles A. Zukowski: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
    Characterization of logic circuit techniques for high leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:230-235 [Conf]
  2. Ali Bastani, Charles A. Zukowski
    Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:119-122 [Conf]
  3. Ali Bastani, Charles A. Zukowski
    Characterization of monotonic static CMOS gates in a 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2005, pp:408-411 [Conf]
  4. Ali Bastani, Charles A. Zukowski
    Monotonic static CMOS tradeoffs in sub-100nm technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:278-283 [Conf]
  5. Gary L. Dare, Charles A. Zukowski
    Accuracy management for mixed-mode digital VLSI simulation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:167-170 [Conf]
  6. Ilias Tagkopoulos, Charles A. Zukowski, German Cavelier, Dimitris Anastassiou
    A custom FPGA for the simulation of gene regulatory networks. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:132-135 [Conf]
  7. Christophe Tretz, Charles A. Zukowski
    CMOS Transistor Sizing for Minimization of Energy-Delay Product. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:168-173 [Conf]
  8. Charles A. Zukowski, George Gristede, Albert E. Ruehli
    Measuring Error Propagation in Waveform Relaxation Algorithms. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:170-173 [Conf]
  9. Hong Shi, Naeem Abbasi, Charles A. Zukowski, Omar Wing
    Buffer size trade-offs in input/output buffered ATM switches under various conditions. [Citation Graph (0, 0)][DBLP]
    ICCCN, 1995, pp:258- [Conf]
  10. Perng-Shyong Lin, Charles A. Zukowski
    Analysis and Control of Timing Jitter in Digital Logic Arising from Noise Voltage Sources. [Citation Graph (0, 0)][DBLP]
    ICCD, 1993, pp:352-356 [Conf]
  11. Charles A. Zukowski, Ying-Wen Bai
    Implementing a High-Frequency Pattern Generator Based on Combinational Merging. [Citation Graph (0, 0)][DBLP]
    ICCD, 1992, pp:81-84 [Conf]
  12. Paul Landsberg, Charles A. Zukowski
    Generic Queue Scheduling: Concepts and VLSI. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1994, pp:1438-1445 [Conf]
  13. Tong-Bi Pei, Charles A. Zukowski
    VLSI Implementation of Routing Tables: Tries and CAMs. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1991, pp:515-524 [Conf]
  14. Hong Shi, Charles A. Zukowski, Omar Wing
    VLSI Design Optimization of Input/Output-Buffered Broadband ATM Switches. [Citation Graph (0, 0)][DBLP]
    INFOCOM, 1996, pp:810-817 [Conf]
  15. Perng-Shyong Lin, Charles A. Zukowski
    Jitter Due to Signal History in Digital Logic Circuits and Its Control Strategies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2114-2117 [Conf]
  16. Ali Bastani, Charles A. Zukowski
    A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:312-317 [Conf]
  17. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
    Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:491-504 [Journal]
  18. Lance A. Glasser, Charles A. Zukowski
    Continuous Models for Communication Density Constraints on Multiprocessor Performance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1988, v:37, n:6, pp:652-656 [Journal]
  19. Jeffrey H. Lang, Charles A. Zukowski, Richard O. LaMaire, Chae H. An
    Integrated-Circuit Logarithmic Arithmetic Units. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:5, pp:475-483 [Journal]
  20. Charles A. Zukowski
    Relaxing Bounds for Linear RC Mesh Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1986, v:5, n:2, pp:305-312 [Journal]

  21. Characteristics of MS-CMOS logic in sub-32nm technologies. [Citation Graph (, )][DBLP]


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