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Publications of Author

1. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
   Characterization of logic circuit techniques for high leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2004, pp:230-235 [Conf]
   
2. George Gristede, Wei Hwang
   A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2000, pp:101-106 [Conf]
   
3. Charles A. Zukowski, George Gristede, Albert E. Ruehli
   Measuring Error Propagation in Waveform Relaxation Algorithms. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1990, pp:170-173 [Conf]
   
4. W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
   Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP]
   ISLPED, 2001, pp:263-266 [Conf]
   
5. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin Warren, Victor V. Zyuban
   Low-power circuits and technology for wireless digital systems. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:283-298 [Journal]
   
6. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
   Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:491-504 [Journal]
   
7. 
   The opportunity cost of low power design: a case study in circuit tuning. [Citation Graph (, )][DBLP]
   
   
8. 
   A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). [Citation Graph (, )][DBLP]