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Stephen V. Kosonocky: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
    Characterization of logic circuit techniques for high leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:230-235 [Conf]
  2. Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu (Jerry) Qi, Mircea R. Stan
    Structured and tuned array generation (STAG) for high-performance random logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:257-262 [Conf]
  3. Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
    Interconnect-centric Array Architectures for Minimum SRAM Access Time. [Citation Graph (0, 0)][DBLP]
    ICCD, 2001, pp:400-405 [Conf]
  4. W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
    Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:263-266 [Conf]
  5. Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
    Understanding and minimizing ground bounce during mode transition of power gating structures. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2003, pp:22-25 [Conf]
  6. Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel, Kevin Stawiasz
    Experimental measurement of a novel power gating structure with intermediate power saving mode. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:20-25 [Conf]
  7. Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown
    Enchanced multi-threshold (MTCMOS) circuits using variable well bias. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:165-169 [Conf]
  8. Victor V. Zyuban, Stephen V. Kosonocky
    Low power integrated scan-retention mechanism. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2002, pp:98-102 [Conf]
  9. Zhenyu (Jerry) Qi, Matthew M. Ziegler, Stephen V. Kosonocky, Jan M. Rabaey, Mircea R. Stan
    Multi-Dimensional Circuit and Micro-Architecture Level Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:275-280 [Conf]
  10. Alice Wang, Anantha Chandrakasan, Stephen V. Kosonocky
    Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2002, pp:7-14 [Conf]
  11. Stephen V. Kosonocky, Arthur A. Bright, Kevin Warren, Ruud A. Haring, Steve Klepner, Sameh W. Asaad, S. Basavaiah, Bob Havreluk, David Heidel, Michael Immediato, Keith A. Jenkins, Rajiv V. Joshi, Ben Parker, T. V. Rajeevakumar, Kevin Stawiasz
    Designing a Testable System on a Chip. [Citation Graph (0, 0)][DBLP]
    VTS, 1998, pp:2-7 [Conf]
  12. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin Warren, Victor V. Zyuban
    Low-power circuits and technology for wireless digital systems. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:283-298 [Journal]
  13. Jean-Olivier Plouchart, Noah Zamdmer, Jonghae Kim, Melanie Sherony, Yue Tan, Asit Ray, Mohamed Talbi, Lawrence F. Wagner, Kun Wu, Naftali E. Lustig, Shreesh Narasimha, Patricia O'Neil, Nghia Phan, Michael Rohn, James Strom, David M. Friend, Stephen V. Kosonocky, Daniel R. Knebel, Suhwan Kim, Keith A. Jenkins, Michel M. Rivier
    Application of an SOI 0.12-µm CMOS technology to SoCs with low-power and high-frequency circuits. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:5-6, pp:611-630 [Journal]
  14. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
    Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:491-504 [Journal]
  15. Gila Kamhi, Sarah Miller, Stephen Bailey Mentor, Wolfgang H. Nebel, Y. C. Wong, Juergen Karmann, Enrico Macii, Stephen V. Kosonocky, Steve Curtis
    Early Power-Aware Design & Validation: Myth or Reality? [Citation Graph (0, 0)][DBLP]
    DAC, 2007, pp:210-211 [Conf]

  16. Keeping hot chips cool: are IC thermal problems hot air? [Citation Graph (, )][DBLP]


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