The SCEAS System
Navigation Menu

Search the dblp DataBase


A. Bellaouar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan
    Circuit/architecture for low-power high-performance 32-bit adder. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1995, pp:74-0 [Conf]
  2. Sher Jiun Fang, See Taur Lee, David J. Allstot, A. Bellaouar
    A 2 GHz CMOS even harmonic mixer for direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:807-810 [Conf]
  3. F. Dulger, Sher Jiun Fang, A. N. Mohieldin, P. Fontaine, A. Bellaouar, M. Frechette
    A quad-band receiver for GSM/GPRS/EDGE in 90 nm digital CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

Search in 0.001secs, Finished in 0.001secs
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
System created by [] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002