The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Altan Odabasioglu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Emrah Acar, Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    S2P: A Stable 2-Pole RC Delay and Coupling Noise Metric. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:60-63 [Conf]
  2. Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    PRIMA: passive reduced-order interconnect macromodeling algorithm. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1997, pp:58-65 [Conf]
  3. Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    Practical considerations for passive reduction of RLC circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1999, pp:214-220 [Conf]
  4. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    Overcoming wireload model uncertainty during physical design. [Citation Graph (0, 0)][DBLP]
    ISPD, 2001, pp:182-189 [Conf]
  5. Padmini Gopalakrishnan, Altan Odabasioglu, Lawrence T. Pileggi, Salil Raje
    An analysis of the wire-load model uncertainty problem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2002, v:21, n:1, pp:23-31 [Journal]
  6. Altan Odabasioglu, Mustafa Celik, Lawrence T. Pileggi
    PRIMA: passive reduced-order interconnect macromodeling algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1998, v:17, n:8, pp:645-654 [Journal]

Search in 0.001secs, Finished in 0.002secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002