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Jeff Draper: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
    2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:198-203 [Conf]
  2. Riaz Naseer, Jeff Draper, Younes Boulghassoul, Sandeepan DasGupta, Art Witulski
    Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:227-230 [Conf]
  3. Riaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski
    Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1879-1882 [Conf]
  4. Riaz Naseer, Jeff Draper
    DF-DICE: a scalable solution for soft error tolerant circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  5. Rashed Zafar Bhatti, Monty Denneau, Jeff Draper
    Phase measurement and adjustment of digital signals using random sampling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  6. The effect of design parameters on single-event upset sensitivity of MOS current mode logic. [Citation Graph (, )][DBLP]


  7. Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers. [Citation Graph (, )][DBLP]


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