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Azeez J. Bhavnagarwala:
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Publications of Author
- Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl
CMOS system-on-a-chip voltage scaling beyond 50nm. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2000, pp:7-12 [Conf]
- Azeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl
Interconnect-centric Array Architectures for Minimum SRAM Access Time. [Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:400-405 [Conf]
- Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl
Minimum supply voltage for bulk Si CMOS GSI. [Citation Graph (0, 0)][DBLP] ISLPED, 1998, pp:100-102 [Conf]
- Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl
Circuit techniques for low-power CMOS GSI. [Citation Graph (0, 0)][DBLP] ISLPED, 1996, pp:193-196 [Conf]
- Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin Warren, Victor V. Zyuban
Low-power circuits and technology for wireless digital systems. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:283-298 [Journal]
- Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl
A minimum total power methodology for projecting limits on CMOS GSI. [Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2000, v:8, n:3, pp:235-251 [Journal]
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