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Massimo Alioto: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Massimo Alioto, Gaetano Palumbo
    Novel Simple Models Of Cml Propagation Delay. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:270-274 [Conf]
  2. Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli
    An approach to the design of PFSCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2437-2440 [Conf]
  3. Massimo Alioto, Gaetano Palumbo
    Design of MUX, XOR and D-latch SCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:261-264 [Conf]
  4. Massimo Alioto, Gaetano Palumbo
    Design techniques for low-power cascaded CML gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:4685-4688 [Conf]
  5. Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
    Long period pseudo random bit generators derived from a discretized chaotic map. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2005, pp:892-895 [Conf]
  6. Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
    CML ring oscillators: oscillation frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:112-115 [Conf]
  7. Massimo Alioto, Ada Fort, Luca Pancioni, Santina Rocchi, Valerio Vignoli
    Positive-Feedback Source-Coupled Logic: a delay model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:641-644 [Conf]
  8. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    A gate-level strategy to design Carry Select Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:465-468 [Conf]
  9. Massimo Alioto, Gaetano Palumbo
    Power-delay trade-offs in SCL gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:249-252 [Conf]
  10. Massimo Alioto, Gaetano Palumbo
    Modeling of Power Consumption of Adiabatic Gates versus Fan in and Comparison with Conventional Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2000, pp:265-275 [Conf]
  11. Massimo Alioto, Gaetano Palumbo
    Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:429-437 [Conf]
  12. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    An Approach to Energy Consumption Modeling in RC Ladder Circuits. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2002, pp:239-246 [Conf]
  13. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits with Exponential Inputs: An Analytical Model. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2005, pp:355-363 [Conf]
  14. Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
    Power Modeling of Precharged Address Bus and Application to Multi-bit DPA Attacks to DES Algorithm. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:593-602 [Conf]
  15. Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
    Techniques to Enhance the Resistance of Precharged Busses to Differential Power Analysis. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:624-633 [Conf]
  16. Massimo Alioto, Rosario Mita, Gaetano Palumbo
    Performance evaluation of the low-voltage CML D-latch topology. [Citation Graph (0, 0)][DBLP]
    Integration, 2003, v:36, n:4, pp:191-209 [Journal]
  17. Massimo Alioto, Gaetano Palumbo
    Highly accurate and simple models for CML and ECL gates. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1999, v:18, n:9, pp:1369-1375 [Journal]
  18. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Evaluation of energy consumption in RC ladder circuits driven by a ramp input. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:10, pp:1094-1107 [Journal]
  19. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Energy Consumption in RC Tree Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:5, pp:452-461 [Journal]
  20. Massimo Alioto, Gaetano Palumbo
    High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus Technology. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2998-3001 [Conf]
  21. Massimo Alioto, Gaetano Palumbo
    Design of Fast Large Fan-In CMOS Multiplexers Accounting for Interconnects. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3255-3258 [Conf]
  22. Massimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli
    Mixed Techniques to Protect Precharged Busses against Differential Power Analysis Attacks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:861-864 [Conf]
  23. Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
    Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional Map. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:693-696 [Conf]
  24. Massimo Alioto, Gaetano Palumbo
    Delay uncertainty due to supply variations in static and dynamic full adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  25. Massimo Alioto, Gaetano Palumbo
    Delay Variability Due to Supply Variations in Transmission-Gate Full Adders. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3732-3735 [Conf]
  26. Tommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli
    A technique to design high entropy chaos-based true random bit generators. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Massimo Alioto, Luca Pancioni, Santina Rocchi, Valerio Vignoli
    Analysis and design of MCML gates with hysteresis. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Massimo Alioto, Gaetano Palumbo
    Nanometer MCML gates: models and design considerations. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  29. Massimo Alioto, Gaetano Palumbo, Massimo Poli
    Efficient output transition time modeling in CMOS gates with ramp/exponential inputs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  30. Massimo Alioto, Gaetano Palumbo
    Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2006, v:14, n:12, pp:1322-1335 [Journal]
  31. Massimo Alioto, Gaetano Palumbo
    Power estimation in adiabatic circuits: a simple and accurate model. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2001, v:9, n:5, pp:608-615 [Journal]
  32. Massimo Alioto, Gaetano Palumbo
    Analysis and comparison on full adder block in submicron technology. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2002, v:10, n:6, pp:806-823 [Journal]

  33. Analysis and performance evaluation of area-efficient true random bit generators on FPGAs. [Citation Graph (, )][DBLP]


  34. A general model for differential power analysis attacks to static logic circuits. [Citation Graph (, )][DBLP]


  35. Power-delay optimization in MCML tapered buffers. [Citation Graph (, )][DBLP]


  36. Explicit energy evaluation in RLC tree circuits with ramp inputs. [Citation Graph (, )][DBLP]


  37. Improving the power-delay product in SCL circuits using source follower output stage. [Citation Graph (, )][DBLP]


  38. Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic. [Citation Graph (, )][DBLP]


  39. Design and Evaluation of Mixed 3T-4T FinFET Stacks for Leakage Reduction. [Citation Graph (, )][DBLP]


  40. Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. [Citation Graph (, )][DBLP]


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