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Elizabeth J. Brauer :
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Elizabeth J. Brauer , Pradeep Elamanchili A Full-Swing Bootstrapped BiCMOS Buffer. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:8-13 [Conf ] Elizabeth J. Brauer , Ranu Jung , Denise M. Wilson , James J. Abbas Analog Circuit Model of Lamprey Unit Pattern Generator. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1997, pp:137-142 [Conf ] Elizabeth J. Brauer , Sung-Mo Kang Functional Verification of ECL Circuits Including Voltage Regulators. [Citation Graph (0, 0)][DBLP ] ISCAS, 1993, pp:1710-1713 [Conf ] Elizabeth J. Brauer , Sung-Mo Kang Estimating Node Voltages in Bipolar Circuits Using Linear Programming. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:901-903 [Conf ] Elizabeth J. Brauer , Sung-Mo Kang An Analytic Method to Calculate Emitter Follower Delay Using Trial Functions in Coupled Node Equations. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:1580-1583 [Conf ] Elizabeth J. Brauer , Yusuf Leblebici Low noise MCML prefix adders using 0.18 µm CMOS technology. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2004, pp:467-470 [Conf ] Elizabeth J. Brauer , Yusuf Leblebici Sub-70 PS full adder IN 0.18 µm CMOS current-mode logic. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2004, pp:483-487 [Conf ] Elizabeth J. Brauer , Vikram Magoon Finding efficient inductor geometries in digital CMOS process for RF applications. [Citation Graph (0, 0)][DBLP ] Circuits, Signals, and Systems, 2004, pp:558-561 [Conf ] Elizabeth J. Brauer , Sung-Mo Kang An algorithm for functional verification of digital ECL circuits. [Citation Graph (0, 0)][DBLP ] IEEE Trans. on CAD of Integrated Circuits and Systems, 1995, v:14, n:12, pp:1546-1556 [Journal ] Elizabeth J. Brauer , Ilhan Hatirnaz , Stéphane Badel , Yusuf Leblebici Via-programmable expanded universal logic gate in MCML for structured ASIC applications: circuit design. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Stéphane Badel , Ilhan Hatirnaz , Yusuf Leblebici , Elizabeth J. Brauer Implementation of Structured ASIC Fabric Using Via-Programmable Differential MCML Cells. [Citation Graph (0, 0)][DBLP ] VLSI-SoC, 2006, pp:234-238 [Conf ] Improving the power-delay product in SCL circuits using source follower output stage. [Citation Graph (, )][DBLP ] Improving the Power-Delay Performance in Subthreshold Source-Coupled Logic Circuits. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.004secs