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Hung Tien Bui: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hung Tien Bui, Yvon Savaria
    High speed differential pulse-width control loop based on frequency-to-voltage converters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:53-56 [Conf]
  2. Hung Tien Bui, Yvon Savaria
    Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:369-372 [Conf]
  3. Hung Tien Bui, Yvon Savaria
    10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2004, pp:115-118 [Conf]
  4. Hung Tien Bui, Yvon Savaria
    A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs. [Citation Graph (0, 0)][DBLP]
    IWSOC, 2005, pp:557-562 [Conf]
  5. Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria
    A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:633-636 [Conf]
  6. Hung Tien Bui
    Dual-Path and Diode-Tracking Active Inductors for MCML Gates. [Citation Graph (0, 0)][DBLP]
    CCECE, 2006, pp:1060-1063 [Conf]

  7. Design of an all-digital variable length ring oscillator (VLRO) for clock synthesis. [Citation Graph (, )][DBLP]

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