The SCEAS System
Navigation Menu

Search the dblp DataBase

Title:
Author:

Mohamed Nekili: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Falah R. Awwad, Mohamed Nekili
    Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:118-123 [Conf]
  2. Mohamed Nekili, Yvon Savaria, Guy Bois
    Design of Clock Distribution Networks in Presence of Process Variations. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1998, pp:95-102 [Conf]
  3. Adhir Upadhyay, Syed Rafay Hasan, Mohamed Nekili
    Optimal partitioning of globally asychronous locally synchronous processor arrays. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2004, pp:7-12 [Conf]
  4. Mohamed Nekili, Yvon Savaria
    Parallel Regeneration of Interconnections in VLSI & ULSI Circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:2023-2026 [Conf]
  5. Mohamed Nekili, Yvon Savaria, Guy Bois
    A Fast Low-Power Driver for Long Interconnections in VLSI Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:343-346 [Conf]
  6. Mohamed Nekili, Yvon Savaria, Guy Bois
    Minimizing process-induced skew using delay tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:426-429 [Conf]
  7. Bill Pontikakis, Mohamed Nekili
    A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:101-104 [Conf]
  8. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Quadratic deferred-merge embedding algorithm for zero skew clock distribution network. [Citation Graph (0, 0)][DBLP]
    Timing Issues in the Specification and Synthesis of Digital Systems, 2002, pp:119-125 [Conf]
  9. Haydar Saaied, Dhamin Al-Khalili, Asim J. Al-Khalili, Mohamed Nekili
    Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 2005, v:24, n:10, pp:1637-1643 [Journal]
  10. Mohamed Nekili, Guy Bois, Yvon Savaria
    Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1997, v:5, n:2, pp:161-174 [Journal]

  11. A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. [Citation Graph (, )][DBLP]


Search in 0.003secs, Finished in 0.003secs
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002