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Gabriel P. Bischoff: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton
    Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:1-6 [Conf]
  2. Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff
    Automatic Detection of MOS Synchronizers for Timing Verification. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1991, pp:304-307 [Conf]
  3. Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich
    Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. [Citation Graph (0, 0)][DBLP]
    ICCAD, 1990, pp:62-65 [Conf]
  4. Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan
    Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:16-24 [Conf]
  5. Gabriel P. Bischoff, Karl S. Brace, Gianpiero Cabodi, Sergio Nocco, Stefano Quer
    Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking. [Citation Graph (0, 0)][DBLP]
    Electr. Notes Theor. Comput. Sci., 2005, v:119, n:2, pp:33-49 [Journal]
  6. Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich
    Clock suppression techniques for synchronous circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1993, v:12, n:10, pp:1547-1556 [Journal]
  7. Gabriel P. Bischoff, Karl S. Brace, Gianpiero Cabodi
    A Compositional Approach for Equivalence Checking of Sequential Circuits with Unknown Reset State and Overlapping Partitions. [Citation Graph (0, 0)][DBLP]
    EUROCAST, 2007, pp:505-514 [Conf]

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