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Yun-Nan Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Yun-Nan Chang, Ching-Yi Wang, Keshab K. Parhi
    Loop-List Scheduling for Heterogeneous Functional Units. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:2-7 [Conf]
  2. Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi
    Design and Implementation of Low-Power Digit-Serial Multipliers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:186-195 [Conf]
  3. Janardhan H. Satyanarayana, Keshab K. Parhi, Leilei Song, Yun-Nan Chang
    Systematic analysis of bounds on power consumption in pipelined and non-pipelined multipliers. [Citation Graph (0, 0)][DBLP]
    ICCD, 1996, pp:492-499 [Conf]
  4. Yun-Nan Chang
    Design of soft-output Viterbi decoders with hybrid trace-back processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2003, pp:69-72 [Conf]
  5. Yun-Nan Chang
    Design of an efficient memory-based DVB-T channel decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2005, pp:5019-5022 [Conf]

  6. An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. [Citation Graph (, )][DBLP]


  7. A Lossless Buffer Compression Scheme for 3D Graphic System. [Citation Graph (, )][DBLP]


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