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Edgar Sánchez-Sinencio: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ahmed Emira, Edgar Sánchez-Sinencio
    Variable gain amplifier with offset cancellation. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2003, pp:265-268 [Conf]
  2. Ahmed Emira, Edgar Sánchez-Sinencio
    A low-power CMOS complex filter for Bluetooth with frequency tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2003, pp:489-492 [Conf]
  3. Xiaohua Fan, Chinmaya Mishra, Edgar Sánchez-Sinencio
    Single Miller capacitor compensated multistage amplifiers for large capacitive load applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:493-496 [Conf]
  4. Apollo Q. Fong, Ajay Kanji, Edgar Sánchez-Sinencio, José Pineda de Gyvez
    A Universal Interface Between PC and Neural Networks Hardware. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1169-1172 [Conf]
  5. Gabriel J. Gómez, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, Martin C. Lefebvre
    A Nonlinear Macromodel for CMOS OTAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:920-923 [Conf]
  6. Gunhee Han, Edgar Sánchez-Sinencio
    A General Purpose Discrete-Time Multiplexing Neuron-Array Architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1320-1323 [Conf]
  7. Joseph T. Nabicht, Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo
    A Programmable 1.8-18MHz High-Q Fully-Differential Continuous-Time Filter with 1.5-2 Power Supply. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:653-656 [Conf]
  8. Jaime Ramírez-Angulo, Edgar Sánchez-Sinencio
    High Frequency Compensated Current-mode Ladder Filters Using Multiple Output OTAs. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1412-1415 [Conf]
  9. Jaime Ramírez-Angulo, Edgar Sánchez-Sinencio
    Two Approaches for Current-Mode Filters using Voltage Follower and Transconductance Multipliers Building Blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1994, pp:669-672 [Conf]
  10. Jaime Ramírez-Angulo, Roberto Sadkowski, Edgar Sánchez-Sinencio
    Linearity, Accuracy and Bandwidth Considerations in Wideband CMOS Voltage Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1251-1254 [Conf]
  11. Sterling L. Smith, Edgar Sánchez-Sinencio
    3v High-frequency Current-mode Filters. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1993, pp:1459-1462 [Conf]
  12. Stanislaw Szczepanski, Slawomir Koziel, Edgar Sánchez-Sinencio
    Linearized CMOS OTA using active-error feedforward technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:549-552 [Conf]
  13. Ari Y. Valero-López, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
    Frequency synthesizer for on-chip testing and automated tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:565-568 [Conf]
  14. Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
    A constant-g/sub m/ rail-to-rail op amp input stage using dynamic current scaling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2567-2570 [Conf]
  15. Shouli Yan, Jingyu Hu, Tongyu Song, Edgar Sánchez-Sinencio
    Constant-g/sub m/ techniques for rail-to-rail CMOS amplifier input stages: a comparative study. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2571-2574 [Conf]
  16. Chunyu Xin, Edgar Sánchez-Sinencio
    A linearization technique for RF low noise amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2004, pp:313-316 [Conf]
  17. Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio, A. Ganesan
    A Design Scheme to Stabilize the Active Gain Enhancement Amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS, 1995, pp:1976-1979 [Conf]
  18. Feng Zhu, Shouli Yan, Jingyu Hu, Edgar Sánchez-Sinencio
    Feedforward reversed nested Miller compensation techniques for three-stage amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2005, pp:2575-2578 [Conf]
  19. A. Shankar, José Silva-Martínez, Edgar Sánchez-Sinencio
    A low voltage operational transconductance amplifier using common mode feedforward for high frequency switched capacitor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:643-646 [Conf]
  20. F. Lobato-Lopez, José Silva-Martínez, Edgar Sánchez-Sinencio
    Linear cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:437-440 [Conf]
  21. G. Xu, Sherif H. K. Embabi, P. Hao, Edgar Sánchez-Sinencio
    A low voltage fully differential nested Gm capacitance compensation amplifier: analysis and design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:606-609 [Conf]
  22. O. A. Gonzalez, Gunhee Han, José Pineda de Gyvez, Edgar Sánchez-Sinencio
    CMOS cryptosystem using a Lorenz chaotic oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 1999, pp:442-445 [Conf]
  23. Chunyu Xin, Bo Xia, Wenjun Sheng, Ari Y. Valero-López, Edgar Sánchez-Sinencio
    A mixed-mode IF GFSK demodulator for Bluetooth. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:457-460 [Conf]
  24. K. Shu, Edgar Sánchez-Sinencio
    A 5-GHz prescaler using improved phase switching. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2002, pp:85-88 [Conf]
  25. K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez
    A 2.1-GHz monolithic frequency synthesizer with robust phase switching prescaler and loop capacitance scaling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:791-794 [Conf]
  26. Ahmed Emira, Edgar Sánchez-Sinencio, M. Schneider
    Design tradeoffs of CMOS current mirrors using one-equation for all-region model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:45-48 [Conf]
  27. Bo Xia, Shouli Yan, E. Sanchez-Sinencio
    An auto-tuning structure for continuous time sigma-delta AD converter and high precision filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:593-596 [Conf]
  28. P. Kallam, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
    An improved Q-tuning scheme and a fully symmetric OTA. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:165-168 [Conf]
  29. Marcia G. Méndez-Rivera, José Silva-Martínez, Edgar Sánchez-Sinencio
    On-chip spectrum analyzer for built-in testing analog ICs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2002, pp:61-64 [Conf]
  30. Fan You, Sherif H. K. Embabi, Edgar Sánchez-Sinencio
    A 1.5V class AB output buffer. [Citation Graph (0, 0)][DBLP]
    ISLPED, 1996, pp:285-288 [Conf]
  31. Antonio F. Mondragón-Torres, Terry Mayhugh Jr., José Pineda de Gyvez, José Silva-Martínez, Edgar Sánchez-Sinencio
    An Analog Integrated Circuit Design Laboratory. [Citation Graph (0, 0)][DBLP]
    MSE, 2003, pp:91-92 [Conf]
  32. Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
    An On-Chip Transfer Function Characterization System for Analog Built-in Testing. [Citation Graph (0, 0)][DBLP]
    VTS, 2004, pp:261-266 [Conf]
  33. Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio
    A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    VTS, 2005, pp:249-254 [Conf]
  34. Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
    On-Chip Testing Techniques for RF Wireless Transceivers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2006, v:23, n:4, pp:268-277 [Journal]
  35. Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo
    AROMA: An Area Optimized CAD Program for Cascade SC Filter Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1985, v:4, n:3, pp:296-303 [Journal]
  36. Rangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio
    A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver Applications. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:429-432 [Conf]
  37. Burak Kelleci, Edgar Sánchez-Sinencio, Aydin I. Karsilayan
    THD+Noise Estimation in Class-D Amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:465-468 [Conf]
  38. Y. He, Ugur Çilingiroglu, Edgar Sánchez-Sinencio
    A high-density and low-power charge-based Hamming network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1993, v:1, n:1, pp:56-62 [Journal]
  39. Lei Wang, José Pineda de Gyvez, Edgar Sánchez-Sinencio
    Time multiplexed color image processing based on a CNN with cell-state outputs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 1998, v:6, n:2, pp:314-322 [Journal]
  40. Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
    An On-Chip Spectrum Analyzer for Analog Built-In Testing. [Citation Graph (0, 0)][DBLP]
    J. Electronic Testing, 2005, v:21, n:3, pp:205-219 [Journal]

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