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Paul Ampadu :
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Bo Fu , Qiaoyan Yu , Paul Ampadu Energy-delay minimization in nanoscale domino logic. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2006, pp:316-319 [Conf ] Bo Fu , Paul Ampadu Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:1173-1176 [Conf ] David Wolpert , Paul Ampadu Temperature-Robust Performance Yield through Supply Voltage Selection. [Citation Graph (0, 0)][DBLP ] ISCAS, 2007, pp:2279-2282 [Conf ] Paul Ampadu Ultra-low voltage VLSI: are we there yet? [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Bo Fu , Paul Ampadu Techniques for robust energy efficient subthreshold domino CMOS circuits. [Citation Graph (0, 0)][DBLP ] ISCAS, 2006, pp:- [Conf ] Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise Environment. [Citation Graph (, )][DBLP ] Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects. [Citation Graph (, )][DBLP ] A Low-Power Safety Mode for Variation Tolerant Systems-on-Chip. [Citation Graph (, )][DBLP ] A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits. [Citation Graph (, )][DBLP ] Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip. [Citation Graph (, )][DBLP ] Adaptive error control for reliable systems-on-chip. [Citation Graph (, )][DBLP ] Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design. [Citation Graph (, )][DBLP ] Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. [Citation Graph (, )][DBLP ] Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip. [Citation Graph (, )][DBLP ] Configurable error correction for multi-wire errors in switch-to-switch SOC links. [Citation Graph (, )][DBLP ] A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes. [Citation Graph (, )][DBLP ] A Dual-Mode Hybrid ARQ Scheme for Energy Efficient On-Chip Interconnects. [Citation Graph (, )][DBLP ] Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates. [Citation Graph (, )][DBLP ] Search in 0.001secs, Finished in 0.002secs