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Wei Hwang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. George Gristede, Wei Hwang
    A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:101-106 [Conf]
  2. Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
    SOI for asynchronous dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2001, pp:37-42 [Conf]
  3. Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
    A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:712-717 [Conf]
  4. W. K. Luk, Y. Katayama, Wei Hwang, M. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
    Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. [Citation Graph (0, 0)][DBLP]
    ICCD, 1997, pp:279-285 [Conf]
  5. Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
    Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:444-447 [Conf]
  6. W. Chen, Wei Hwang, P. Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
    Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2001, pp:263-266 [Conf]
  7. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
    "Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). [Citation Graph (0, 0)][DBLP]
    ISLPED, 2000, pp:203-206 [Conf]
  8. Rajiv V. Joshi, Wei Hwang
    Design Considerations and Implementation of a High Performance Dynamic Register File. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 1999, pp:526-531 [Conf]
  9. Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
    Design Of Provably Correct Storage Arrays. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2001, pp:196-0 [Conf]
  10. Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
    A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2000, pp:44-49 [Conf]
  11. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin Warren, Victor V. Zyuban
    Low-power circuits and technology for wireless digital systems. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2003, v:47, n:2-3, pp:283-298 [Journal]
  12. Ming-Hung Chang, Zong-Xi Yang, Wei Hwang
    A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1137-1140 [Conf]
  13. Wei-Chih Hsieh, Wei Hwang
    Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1637-1640 [Conf]
  14. Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
    A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  15. Po-Tsang Huang, Wei Hwang
    2-level FIFO architecture design for switch fabrics in network-on-chip. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  16. Tzu-Chiang Chao, Wei Hwang
    A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  17. A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. [Citation Graph (, )][DBLP]

  18. "Green" micro-architecture and circuit co-design for ternary content addressable memory. [Citation Graph (, )][DBLP]

  19. Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. [Citation Graph (, )][DBLP]

  20. Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. [Citation Graph (, )][DBLP]

  21. On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. [Citation Graph (, )][DBLP]

  22. A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. [Citation Graph (, )][DBLP]

  23. In-situ self-aware adaptive power control system with multi-mode power gating network. [Citation Graph (, )][DBLP]

  24. A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. [Citation Graph (, )][DBLP]

  25. A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. [Citation Graph (, )][DBLP]

  26. Low-power floating bitline 8-T SRAM design with write assistant circuits. [Citation Graph (, )][DBLP]

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