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Kwang Sub Yoon :
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Yun Cheol Han , Kwang il Kim , Jun Kim , Kwang Sub Yoon A dual band CMOS VCO with a balanced duty cycle buffer. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2003, pp:277-280 [Conf ] Jai-Sop Hyun , Kwang Sub Yoon A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. [Citation Graph (0, 0)][DBLP ] Great Lakes Symposium on VLSI, 1996, pp:260-0 [Conf ] Jong Kug Seon , Kwang Sub Yoon A Precision Output Conductance Model for Analog CMOS Circuit Simulations. [Citation Graph (0, 0)][DBLP ] ISCAS, 1995, pp:1584-1587 [Conf ] Hyuk-Jun Sung , Kwang Sub Yoon A 3.3 V high speed CMOS PLL with 3-250 MHz input locking range. [Citation Graph (0, 0)][DBLP ] ISCAS (2), 1999, pp:553-556 [Conf ] Soo Jin Park , Byoung Hee Yoon , Kwang Sub Yoon , Heung Soo Kim Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit. [Citation Graph (0, 0)][DBLP ] ISMVL, 2004, pp:198-203 [Conf ] Search in 0.001secs, Finished in 0.001secs