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Ajay Joshi :
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Ajay Joshi , Jeffrey A. Davis Wave-pipelined 2-slot time division multiplexed (WP/2-TDM) routing. [Citation Graph (0, 0)][DBLP ] ACM Great Lakes Symposium on VLSI, 2005, pp:446-451 [Conf ] Ajay Joshi , Jeffrey A. Davis A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP ] SLIP, 2004, pp:64-68 [Conf ] Ajay Joshi , Vinita V. Deodhar , Jeffrey A. Davis Low Power Multilevel Interconnect Networks Using Wave-Pipelined Multiplexed (WPM) Routing. [Citation Graph (0, 0)][DBLP ] VLSI Design, 2006, pp:773-776 [Conf ] Ajay Joshi , Aashish Phansalkar , Lieven Eeckhout , Lizy Kurian John Measuring Benchmark Similarity Using Inherent Program Characteristics. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2006, v:55, n:6, pp:769-782 [Journal ] Ajay Joshi , Jeffrey A. Davis Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2005, v:13, n:8, pp:899-910 [Journal ] Aashish Phansalkar , Ajay Joshi , Lizy Kurian John Analysis of redundancy and application balance in the SPEC CPU2006 benchmark suite. [Citation Graph (0, 0)][DBLP ] ISCA, 2007, pp:412-423 [Conf ] Ajay Joshi , Lieven Eeckhout , Robert H. Bell Jr. , Lizy Kurian John Performance Cloning: A Technique for Disseminating Proprietary Applications as Benchmarks. [Citation Graph (0, 0)][DBLP ] IISWC, 2006, pp:105-115 [Conf ] Joshua J. Yi , Resit Sendag , Lieven Eeckhout , Ajay Joshi , David J. Lilja , Lizy Kurian John Evaluating Benchmark Subsetting Approaches. [Citation Graph (0, 0)][DBLP ] IISWC, 2006, pp:93-104 [Conf ] Ajay Joshi , Yue Luo , Lizy K. John Applying Statistical Sampling for Fast and Efficient Simulation of Commercial Workloads. [Citation Graph (0, 0)][DBLP ] IEEE Trans. Computers, 2007, v:56, n:11, pp:1520-1533 [Journal ] Ajay Joshi , Gerald G. Lopez , Jeffrey A. Davis Design and Optimization of On-Chip Interconnects Using Wave-Pipelined Multiplexed Routing. [Citation Graph (0, 0)][DBLP ] IEEE Trans. VLSI Syst., 2007, v:15, n:9, pp:990-1002 [Journal ] Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. [Citation Graph (, )][DBLP ] Design of Reliable and Secure Multipliers by Multilinear Arithmetic Codes. [Citation Graph (, )][DBLP ] Designing multi-socket systems using silicon photonics. [Citation Graph (, )][DBLP ] Re-architecting DRAM memory systems with monolithically integrated silicon photonics. [Citation Graph (, )][DBLP ] Evaluating the efficacy of statistical simulation for design space exploration. [Citation Graph (, )][DBLP ] Measuring Program Similarity: Experiments with SPEC CPU Benchmark Suites. [Citation Graph (, )][DBLP ] Analyzing and Improving Clustering Based Sampling for Microprocessor Simulation. [Citation Graph (, )][DBLP ] A Modeling and exploration framework for interconnect network design in the nanometer era. [Citation Graph (, )][DBLP ] Silicon-photonic clos networks for global on-chip communication. [Citation Graph (, )][DBLP ] Automatically countering imbalance and its empirical relationship to cost. [Citation Graph (, )][DBLP ] Search in 0.003secs, Finished in 0.004secs