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Volkan Kursun: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ranjith Kumar, Volkan Kursun
    A design methodology for temperature variation insensitive low power circuits. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:410-415 [Conf]
  2. Zhiyu Liu, Volkan Kursun
    Leakage current starved domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:428-433 [Conf]
  3. Volkan Kursun, Eby G. Friedman
    Low swing dual threshold voltage domino logic. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2002, pp:47-52 [Conf]
  4. Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva Narendra
    Cascode buffer for monolithic voltage conversion operating at high input supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:464-467 [Conf]
  5. Volkan Kursun, Eby G. Friedman
    Forward body biased keeper for enhanced noise immunity in domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:917-920 [Conf]
  6. Volkan Kursun, Eby G. Friedman
    Energy efficient dual threshold voltage dynamic circuits employing sleep switches to minimize subthreshold leakage. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2004, pp:417-420 [Conf]
  7. Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald Gardner, Siva Narendra, Tanay Karnik, Vivek De
    Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2004, pp:263-268 [Conf]
  8. Zhiyu Liu, Volkan Kursun
    Robust Dynamic Node Low Voltage Swing Domino Logic with Multiple Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:31-36 [Conf]
  9. Zhiyu Liu, Volkan Kursun
    Leakage Biased Sleep Switch Domino Logic. [Citation Graph (0, 0)][DBLP]
    ISQED, 2006, pp:318-323 [Conf]
  10. Volkan Kursun, Eby G. Friedman
    Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:104-109 [Conf]
  11. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. [Citation Graph (0, 0)][DBLP]
    ISQED, 2003, pp:279-0 [Conf]
  12. Volkan Kursun, Siva Narendra, Vivek De, Eby G. Friedman
    High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. [Citation Graph (0, 0)][DBLP]
    ISQED, 2004, pp:517-521 [Conf]
  13. Zhiyu Liu, Volkan Kursun
    Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:239-244 [Conf]
  14. Sherif A. Tawfik, Volkan Kursun
    Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. [Citation Graph (0, 0)][DBLP]
    ISQED, 2007, pp:73-78 [Conf]
  15. Zhiyu Liu, Volkan Kursun
    High Speed Low Swing Dynamic Circuits with Multiple Supply and Threshold Voltages. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2006, pp:59-64 [Conf]
  16. Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman
    Managing static leakage energy in microprocessor functional units. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:321-332 [Conf]
  17. David H. Albonesi, Rajeev Balasubramonian, Steve Dropsho, Sandhya Dwarkadas, Eby G. Friedman, Michael C. Huang, Volkan Kursun, Grigorios Magklis, Michael L. Scott, Greg Semeraro, Pradip Bose, Alper Buyuktosunoglu, Peter W. Cook, Stanley Schuster
    Dynamically Tuning Processor Resources with Adaptive Processing. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2003, v:36, n:12, pp:49-58 [Journal]
  18. Volkan Kursun, Eby G. Friedman
    Sleep switch dual threshold Voltage domino logic with reduced standby leakage current. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:5, pp:485-496 [Journal]
  19. Zhiyu Liu, Volkan Kursun
    Sleep switch dual threshold voltage domino logic with reduced subthreshold and gate oxide leakage current. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:8, pp:812-820 [Journal]
  20. Volkan Kursun, Vivek De, Eby G. Friedman, Siva G. Narendra
    Monolithic voltage conversion in low-voltage CMOS technologies. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2005, v:36, n:9, pp:863-867 [Journal]
  21. Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu
    Leakage-Aware Design of Nanometer SoC. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3231-3234 [Conf]
  22. Sherif A. Tawfik, Volkan Kursun
    Multi-Vth Level Conversion Circuits for Multi-VDD Systems. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1397-1400 [Conf]
  23. Zhiyu Liu, Volkan Kursun
    High Read Stability and Low Leakage Cache Memory Cell. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:2774-2777 [Conf]
  24. Sherif A. Tawfik, Volkan Kursun
    Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:645-648 [Conf]
  25. Zhiyu Liu, Volkan Kursun
    Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1389-1392 [Conf]
  26. Volkan Kursun, Zhiyu Liu
    Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  27. Ranjith Kumar, Volkan Kursun
    Impact of temperature fluctuations on circuit characteristics in 180nm and 65nm CMOS technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  28. Volkan Kursun, Eby G. Friedman
    Domino logic with variable threshold voltage keeper. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1080-1093 [Journal]
  29. Volkan Kursun, Siva G. Narendra, Vivek De, Eby G. Friedman
    Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2003, v:11, n:3, pp:514-522 [Journal]

  30. Work-function engineering for reduced power and higher integration density: An alternative to sizing for stability in FinFET memory circuits. [Citation Graph (, )][DBLP]


  31. Low power and robust 7T dual-Vt SRAM circuit. [Citation Graph (, )][DBLP]


  32. Dynamic wordline voltage swing for low leakage and stable static memory banks. [Citation Graph (, )][DBLP]


  33. Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. [Citation Graph (, )][DBLP]


  34. Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations. [Citation Graph (, )][DBLP]


  35. Characterization of New Static Independent-Gate-Biased FinFET Latches and Flip-Flops under Process Variations. [Citation Graph (, )][DBLP]


  36. Compact FinFET Memory Circuits with P-Type Data Access Transistors for Low Leakage and Robust Operation. [Citation Graph (, )][DBLP]


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