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Thomas J. Bucelot:
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- Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2005, pp:38-43 [Conf]
- Gregory P. Rodgers, Isidore G. Bendrihem, Thomas J. Bucelot, Barry D. Burchett, John C. Collins
Infrastructure requirements for a large-scale, multi-site VLSI development project. [Citation Graph (0, 0)][DBLP] IBM Journal of Research and Development, 2002, v:46, n:1, pp:87-96 [Journal]
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