|
Search the dblp DataBase
K. Najeeb:
[Publications]
[Author Rank by year]
[Co-authors]
[Prefers]
[Cites]
[Cited by]
Publications of Author
- K. Najeeb, Vishal Gupta, V. Kamakoti
Delay and peak power minimization for on-chip buses using temporal redundancy. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2006, pp:119-122 [Conf]
- K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
Controllability-driven Power Virus Generation for Digital Circuits. [Citation Graph (0, 0)][DBLP] VLSI Design, 2007, pp:407-412 [Conf]
- K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula
Power Virus Generation Using Behavioral Models of Circuits. [Citation Graph (0, 0)][DBLP] VTS, 2007, pp:35-42 [Conf]
- K. Najeeb, Vishal Gupta, V. Kamakoti, Madhu Mutyam
Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses. [Citation Graph (0, 0)][DBLP] J. Low Power Electronics, 2006, v:2, n:3, pp:425-436 [Journal]
Search in 0.001secs, Finished in 0.001secs
|