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## Search the dblp DataBase
Saurabh N. Adya:
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## Publications of Author- David A. Papa, Saurabh N. Adya, Igor L. Markov
**Constructive benchmarking for placement.**[Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2004, pp:113-118 [Conf] - Saurabh N. Adya, S. Chaturvedi, Jarrod A. Roy, David A. Papa, Igor L. Markov
**Unification of partitioning, placement and floorplanning.**[Citation Graph (0, 0)][DBLP] ICCAD, 2004, pp:550-557 [Conf] - Saurabh N. Adya, Igor L. Markov, Paul Villarrubia
**On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis.**[Citation Graph (0, 0)][DBLP] ICCAD, 2003, pp:311-319 [Conf] - Saurabh N. Adya, Igor L. Markov
**Fixed-outline Floorplanning through Better Local Search.**[Citation Graph (0, 0)][DBLP] ICCD, 2001, pp:328-334 [Conf] - Saurabh N. Adya, Igor L. Markov
**Consistent placement of macro-blocks using floorplanning and standard-cell placement.**[Citation Graph (0, 0)][DBLP] ISPD, 2002, pp:12-17 [Conf] - Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
**Benchmarking for large-scale placement and beyond.**[Citation Graph (0, 0)][DBLP] ISPD, 2003, pp:95-103 [Conf] - Hayward H. Chan, Saurabh N. Adya, Igor L. Markov
**Are floorplan representations important in digital design?**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:129-136 [Conf] - Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov
**Capo: robust and scalable open-source min-cut floorplacer.**[Citation Graph (0, 0)][DBLP] ISPD, 2005, pp:224-226 [Conf] - Saurabh N. Adya, Igor L. Markov, Paul G. Villarrubia
**On whitespace and stability in physical synthesis.**[Citation Graph (0, 0)][DBLP] Integration, 2006, v:39, n:4, pp:340-362 [Journal] - Saurabh N. Adya, Mehmet Can Yildiz, Igor L. Markov, Paul Villarrubia, Phiroze N. Parakh, Patrick H. Madden
**Benchmarking for large-scale placement and beyond.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2004, v:23, n:4, pp:472-487 [Journal] - Jarrod A. Roy, Saurabh N. Adya, David A. Papa, Igor L. Markov
**Min-cut floorplacement.**[Citation Graph (0, 0)][DBLP] IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, v:25, n:7, pp:1313-1326 [Journal] - Saurabh N. Adya, Igor L. Markov
**Combinatorial techniques for mixed-size placement.**[Citation Graph (0, 0)][DBLP] ACM Trans. Design Autom. Electr. Syst., 2005, v:10, n:1, pp:58-90 [Journal] - Saurabh N. Adya, Igor L. Markov
**Fixed-outline floorplanning: enabling hierarchical design.**[Citation Graph (0, 0)][DBLP] IEEE Trans. VLSI Syst., 2003, v:11, n:6, pp:1120-1135 [Journal]
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