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Radu M. Secareanu: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Mikhail Popovich, Eby G. Friedman, Michael Sotman, Avinoam Kolodny, Radu M. Secareanu
    Maximum effective distance of on-chip decoupling capacitors in power distribution grids. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2006, pp:173-179 [Conf]
  2. Radu M. Secareanu, Ivan S. Kourtev, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Eby G. Friedman
    Noise Immunity of Digital Circuits in Mixed-Signal Smart Power Systems. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1999, pp:314-317 [Conf]
  3. Radu M. Secareanu, Eby G. Friedman
    Transparent repeaters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2000, pp:63-66 [Conf]
  4. Radu M. Secareanu, S. K. Banerjee, Olin L. Hartin, Francisco V. Fernandez, Eby G. Friedman
    Managing substrate and interconnect noise from high performance repeater insertion in a mixed-signal environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2005, pp:612-615 [Conf]
  5. Radu M. Secareanu, Bill Peterson
    An adaptive circuits concept to address mismatch in analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2004, pp:885-888 [Conf]
  6. Radu M. Secareanu, Eby G. Friedman, Juan Becerra, Scott Warner
    A universal CMOS voltage interface circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 1999, pp:242-245 [Conf]
  7. Radu M. Secareanu, Eby G. Friedman
    A high precision CMOS current mirror/divider. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 1999, pp:314-317 [Conf]
  8. Radu M. Secareanu, Bill Peterson, D. Hartman
    A low-voltage low-noise digital buffer system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2002, pp:181-184 [Conf]
  9. Radu M. Secareanu, Scott Warner, Scott Seabridge, Cathie Burke, Juan Becerra, Thomas E. Watrobski, Christopher Morton, William Staub, Thomas Tellier, Ivan S. Kourtev, Eby G. Friedman
    Substrate coupling in digital circuits in mixed-signal smart-power systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:1, pp:67-78 [Journal]
  10. Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin
    Substrate Noise Reduction Based On Noise Aware Cell Design. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3227-3230 [Conf]
  11. Radu M. Secareanu, Olin L. Hartin
    Low power architectures using localised non-volatile memory and selective power shut-down. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]
  12. Radu M. Secareanu, A. Marshall
    Guest Editorial Special Section on System-on-Chip Integration: Challenges and Implications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2007, v:15, n:10, pp:1065-1066 [Journal]

  13. Contact merging algorithm for efficient substrate noise analysis in large scale circuits. [Citation Graph (, )][DBLP]


  14. Efficient placement of distributed on-chip decoupling capacitors in nanoscale ICs. [Citation Graph (, )][DBLP]


  15. Equivalent rise time for resonance in power/ground noise estimation. [Citation Graph (, )][DBLP]


  16. Input port reduction for efficient substrate extraction in large scale IC's. [Citation Graph (, )][DBLP]


  17. Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates. [Citation Graph (, )][DBLP]


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