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Amara Amara: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Philippe Royannez, Amara Amara
    A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. [Citation Graph (0, 0)][DBLP]
    Great Lakes Symposium on VLSI, 1996, pp:24-28 [Conf]
  2. Erik Rydgren, Thomas Ea, Frederic Amiel, Florence Rossant, Amara Amara
    IRIS features extraction using wavelet packets. [Citation Graph (0, 0)][DBLP]
    ICIP, 2004, pp:861-864 [Conf]
  3. Florence Rossant, Frederic Amiel, Thomas Ea, Amara Amara, Manuel Torres Eslava
    Iris identification and robustness evaluation of a wavelet packets based algorithm. [Citation Graph (0, 0)][DBLP]
    ICIP (3), 2005, pp:257-260 [Conf]
  4. Olivier Thomas, Amara Amara
    An SOI 4 transistors self-refresh ultra-low-voltage memory cell. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2003, pp:401-404 [Conf]
  5. A. Turier, L. Ben Ammar, A. Amara
    Static power consumption management in CMOS memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:506-509 [Conf]
  6. A. Valentian, O. Thomas, Andrei Vladimirescu, Amara Amara
    Modeling subthreshold SOI logic for static timing analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. VLSI Syst., 2004, v:12, n:6, pp:662-669 [Journal]
  7. Amara Amara, Frederic Amiel, Thomas Ea
    FPGA vs. ASIC for low power applications. [Citation Graph (0, 0)][DBLP]
    Microelectronics Journal, 2006, v:37, n:8, pp:669-677 [Journal]
  8. Bastien Giraud, Amara Amara, Andrei Vladimirescu
    A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3022-3025 [Conf]

  9. Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS. [Citation Graph (, )][DBLP]

  10. An Innovative 6T Hybrid SRAM Cell in sub-32 nm Double-Gate MOS Technology. [Citation Graph (, )][DBLP]

  11. Ultra low voltage design considerations of SOI SRAM memory cells. [Citation Graph (, )][DBLP]

  12. A novel 4T asymmetric single-ended SRAM cell in sub-32 nm double gate technology. [Citation Graph (, )][DBLP]

  13. An On-Chip Multi-mode Buck DC-DC Converter for Fine-Grain DVS on a Multi-power Domain SoC Using a 65-nm Standard CMOS Logic Process. [Citation Graph (, )][DBLP]

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