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Publications of Author

1. Tetsuya Uemura, Pinaki Mazumder
   Design and Analysis of a Novel Quantum-MOS Sense Amplifier Circuit. [Citation Graph (0, 0)][DBLP]
   Great Lakes Symposium on VLSI, 1999, pp:158-161 [Conf]
   
2. Tetsuya Uemura, Pinaki Mazumder
   Rise time analysis of MOBILE circuit. [Citation Graph (0, 0)][DBLP]
   ISCAS (5), 2002, pp:864-867 [Conf]
   
3. Toshio Baba, Tetsuya Uemura
   Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits . [Citation Graph (0, 0)][DBLP]
   ISMVL, 1997, pp:41-46 [Conf]
   
4. Toshio Baba, Tetsuya Uemura
   Development of InGaAs-Based Multiple-Junction Surface Tunnel Transistors for Multiple-Valued Logic Circuits. [Citation Graph (0, 0)][DBLP]
   ISMVL, 1998, pp:7-12 [Conf]
   
5. Tetsuya Uemura, Toshio Baba
   Demonstration of a Novel Multiple-Valued T-Gate Using Multiple-Junction Surface Tunnel Transistors and Its Application to Three-Valued Data Flip-Flop. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2000, pp:305-310 [Conf]
   
6. Tetsuya Uemura, Toshio Baba
   A Three-Valued D-Flip-Flop and Shift Register Using Multiple-Junction Surface Tunnel Transistors. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2001, pp:89-93 [Conf]
   
7. Tetsuya Uemura, Masafumi Yamamoto
   Proposal of Four-Valued MRAM based on MTJ/RTD Structure. [Citation Graph (0, 0)][DBLP]
   ISMVL, 2003, pp:273-0 [Conf]
   
8. Shuichi Toyoda, Noboru Niki, Tetsuya Uemura, Hiromu Nishitani
   Clinical support system using information aggregation and visualization for order data. [Citation Graph (0, 0)][DBLP]
   Systems and Computers in Japan, 2005, v:36, n:1, pp:12-24 [Journal]
   
9. 
   Four-State Magnetic Random Access Memory and Ternary Content Addressable Memory Using CoFe-Based Magnetic Tunnel Junctions. [Citation Graph (, )][DBLP]