Search the dblp DataBase

Publications of Author

1. Ou He, Sheqin Dong, Jinian Bian, Yuchun Ma, Xianlong Hong
   An effective buffer planning algorithm for IP based fixed-outline SOC placement. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:564-569 [Conf]
   
2. 
   Symmetry constraint based on mismatch analysis for analog layout in SOI technology. [Citation Graph (, )][DBLP]
   
   
3. 
   Bus via reduction based on floorplan revising. [Citation Graph (, )][DBLP]
   
   
4. 
   A novel fixed-outline floorplanner with zero deadspace for hierarchical design. [Citation Graph (, )][DBLP]