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Sreehari Veeramachaneni: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas
    Novel architectures for efficient (m, n) parallel counters. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:188-191 [Conf]
  2. Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
    Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format. [Citation Graph (0, 0)][DBLP]
    ISVLSI, 2007, pp:343-350 [Conf]
  3. Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
    Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors. [Citation Graph (0, 0)][DBLP]
    VLSI Design, 2007, pp:324-329 [Conf]
  4. Sreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas
    Novel High-Speed Redundant Binary to Binary converter using Prefix Networks. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:3271-3274 [Conf]

  5. A low power, variable resolution two-step flash ADC. [Citation Graph (, )][DBLP]


  6. A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor. [Citation Graph (, )][DBLP]


  7. Design of a Low Power, Variable-Resolution Flash ADC. [Citation Graph (, )][DBLP]


  8. An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects. [Citation Graph (, )][DBLP]


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