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Zohreh Karimi:
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- Shigetoshi Nakatake, Zohreh Karimi, Taraneh Taghavi, Majid Sarrafzadeh
Block placement to ensure channel routability. [Citation Graph (0, 0)][DBLP] ACM Great Lakes Symposium on VLSI, 2007, pp:465-468 [Conf]
- Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi
Utilizing Various ADL Facets for Instruction Level CPU Test. [Citation Graph (0, 0)][DBLP] MTV, 2003, pp:38-0 [Conf]
- Elham Safi, Reihaneh Saberi, Zohreh Karimi, Zainalabedin Navabi
Processor Testing Using an ADL Description and Genetic Algorithms. [Citation Graph (0, 0)][DBLP] VLSI-SOC, 2003, pp:186-0 [Conf]
Power aware placement for FPGAs with dual supply voltages. [Citation Graph (, )][DBLP]
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