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Andrea Calimera: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  2. A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1544-1549 [Conf]

  3. Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints. [Citation Graph (, )][DBLP]


  4. Enabling concurrent clock and power gating in an industrial design flow. [Citation Graph (, )][DBLP]


  5. Post-placement temperature reduction techniques. [Citation Graph (, )][DBLP]


  6. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. [Citation Graph (, )][DBLP]


  7. Temperature-insensitive synthesis using multi-vt libraries. [Citation Graph (, )][DBLP]


  8. NBTI-aware sleep transistor design for reliable power-gating. [Citation Graph (, )][DBLP]


  9. Aging effects of leakage optimizations for caches. [Citation Graph (, )][DBLP]


  10. An integrated thermal estimation framework for industrial embedded platforms. [Citation Graph (, )][DBLP]


  11. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]


  12. Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. [Citation Graph (, )][DBLP]


  13. NBTI-aware power gating for concurrent leakage and aging optimization. [Citation Graph (, )][DBLP]


  14. Dynamic indexing: concurrent leakage and aging optimization for caches. [Citation Graph (, )][DBLP]


  15. Reducing Timing Overhead in Simultaneously Clock-Gated and Power-Gated Designs by Placement-Aware Clustering. [Citation Graph (, )][DBLP]


  16. On-chip Thermal Modeling Based on SPICE Simulation. [Citation Graph (, )][DBLP]


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