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Publications of Author

1. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
   Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
   ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
   
2. Antonio Pullini, Federico Angiolini, Davide Bertozzi, Luca Benini
   Fault tolerance overhead in network-on-chip flow control schemes. [Citation Graph (0, 0)][DBLP]
   SBCCI, 2005, pp:224-229 [Conf]
   
3. Antonio Pullini, Federico Angiolini, Paolo Meloni, David Atienza, Srinivasan Murali, Luigi Raffo, Giovanni De Micheli, Luca Benini
   NoC Design and Implementation in 65nm Technology. [Citation Graph (0, 0)][DBLP]
   NOCS, 2007, pp:273-282 [Conf]
   
4. Antonio Pullini, Federico Angiolini, Srinivasan Murali, David Atienza, Giovanni De Micheli, Luca Benini
   Bringing NoCs to 65 nm. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2007, v:27, n:5, pp:75-85 [Journal]
   
5. 
   Networks on Chips: from research to products. [Citation Graph (, )][DBLP]
   
   
6. 
   A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]
   
   
7. 
   Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]
   
   
8. 
   Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis. [Citation Graph (, )][DBLP]
   
   
9. 
   Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]
   
   
10. 
    On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]
    
    
11. 
    Timing-driven row-based power gating. [Citation Graph (, )][DBLP]
    
    
12. 
    Automatic synthesis of near-threshold circuits with fine-grained performance tunability. [Citation Graph (, )][DBLP]