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Ashoka Visweswara Sathanur: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Andrea Calimera, Antonio Pullini, Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technology. [Citation Graph (0, 0)][DBLP]
    ACM Great Lakes Symposium on VLSI, 2007, pp:501-504 [Conf]
  2. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic thermal clock skew compensation using tunable delay buffers. [Citation Graph (0, 0)][DBLP]
    ISLPED, 2006, pp:162-167 [Conf]
  3. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective. [Citation Graph (0, 0)][DBLP]
    PATMOS, 2006, pp:214-224 [Conf]
  4. A. Sathanur, Andrea Calimera, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing. [Citation Graph (0, 0)][DBLP]
    DATE, 2007, pp:1544-1549 [Conf]
  5. K. Duraisami, Prassanna Sithambaram, A. Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino
    Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock Skew. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2007, pp:1061-1064 [Conf]
  6. Ashutosh Chakraborty, K. Duraisami, Ashoka Visweswara Sathanur, Prassanna Sithambaram, Alberto Macii, Enrico Macii, Massimo Poncino
    Implications of ultra low-voltage devices on design techniques for controlling leakage in NanoCMOS circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS, 2006, pp:- [Conf]

  7. A Scalable Algorithmic Framework for Row-Based Power-Gating. [Citation Graph (, )][DBLP]


  8. Physically clustered forward body biasing for variability compensation in nanometer CMOS design. [Citation Graph (, )][DBLP]


  9. Optimal sleep transistor synthesis under timing and area constraints. [Citation Graph (, )][DBLP]


  10. On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits. [Citation Graph (, )][DBLP]


  11. Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction. [Citation Graph (, )][DBLP]


  12. Timing-driven row-based power gating. [Citation Graph (, )][DBLP]


  13. Automatic synthesis of near-threshold circuits with fine-grained performance tunability. [Citation Graph (, )][DBLP]


  14. Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. [Citation Graph (, )][DBLP]


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