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Siamak Arya: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Siamak Arya, Howard Sachs, Sreeram Duvvuru
    An architecture for high instruction level parallelism. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:153-162 [Conf]
  2. Sreeram Duvvuru, Siamak Arya
    Evaluation of a branch target address cache. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1995, pp:173-180 [Conf]
  3. Siamak Arya, Blaine Gaither
    Parallel algorithm development workbench. [Citation Graph (0, 0)][DBLP]
    SC, 1988, pp:11-17 [Conf]
  4. Siamak Arya
    An Optimal Instruction-Scheduling Model for a Class of Vector Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1985, v:34, n:11, pp:981-995 [Journal]

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