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Pohua P. Chang: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Pohua P. Chang
    Introduction. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:360- [Conf]
  2. Pohua P. Chang, Utpal Banerjee
    Profile-Guided Multi-Heuristic Branch Prediction. [Citation Graph (0, 0)][DBLP]
    ICPP (1), 1995, pp:215-218 [Conf]
  3. Scott A. Mahlke, Nancy J. Warter, William Y. Chen, Pohua P. Chang, Wen-mei W. Hwu
    The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs. [Citation Graph (0, 0)][DBLP]
    ICPP (2), 1991, pp:142-145 [Conf]
  4. William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu, Tokuzo Kiyohara, Pohua P. Chang
    Tolerating data access latency with register preloading. [Citation Graph (0, 0)][DBLP]
    ICS, 1992, pp:104-113 [Conf]
  5. Pohua P. Chang, Wen-mei W. Hwu
    Control flow optimization for supercomputer scalar processing. [Citation Graph (0, 0)][DBLP]
    ICS, 1989, pp:145-153 [Conf]
  6. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    ISCA, 1991, pp:266-275 [Conf]
  7. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu
    IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    25 Years ISCA: Retrospectives and Reprints, 1998, pp:408-417 [Conf]
  8. Wen-mei W. Hwu, Pohua P. Chang
    Exploiting Parallel Microprocessor Microarchitectures With a Compiler Code Generator. [Citation Graph (0, 0)][DBLP]
    ISCA, 1988, pp:45-53 [Conf]
  9. Wen-mei W. Hwu, Pohua P. Chang
    Achieving High Instruction Cache Performance with an Optimizing Compiler. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:242-251 [Conf]
  10. Wen-mei W. Hwu, Thomas M. Conte, Pohua P. Chang
    Comparing Software and Hardware Schemes For Reducing the Cost of Branches. [Citation Graph (0, 0)][DBLP]
    ISCA, 1989, pp:224-233 [Conf]
  11. Pohua P. Chang, Dong-yuan Chen, Yong-Fong Lee, Youfeng Wu, Utpal Banerjee
    Bidirectional Scheduling: A New Global Code Scheduling Approach. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:222-230 [Conf]
  12. David A. Berson, Pohua P. Chang, Rajiv Gupta, Mary Lou Soffa
    Integrating Program Optimizations and Transformations with the Scheduling of Instruction Level Parallelism. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:207-221 [Conf]
  13. K. Sridharan, Pohua P. Chang, Utpal Banerjee, Ravi Narayanaswamy, Suresh Rao
    Memory Optimizations in the Intel Reference Compiler. [Citation Graph (0, 0)][DBLP]
    LCPC, 1996, pp:608-610 [Conf]
  14. James Radigan, Pohua P. Chang, Utpal Banerjee
    Integer Loop Code Generation for VLIW. [Citation Graph (0, 0)][DBLP]
    LCPC, 1995, pp:318-330 [Conf]
  15. Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu
    Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:25-33 [Conf]
  16. Pohua P. Chang, Wen-mei W. Hwu
    Trace selection for compiling large C application programs to microcode. [Citation Graph (0, 0)][DBLP]
    MICRO, 1988, pp:21-29 [Conf]
  17. William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu
    Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. [Citation Graph (0, 0)][DBLP]
    MICRO, 1991, pp:69-73 [Conf]
  18. Wen-mei W. Hwu, Pohua P. Chang
    Inline Function Expansion for Compiling C Programs. [Citation Graph (0, 0)][DBLP]
    PLDI, 1989, pp:246-257 [Conf]
  19. Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Profile-guided Automatic Inline Expansion for C Programs. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1992, v:22, n:5, pp:349-369 [Journal]
  20. Pohua P. Chang, Scott A. Mahlke, Wen-mei W. Hwu
    Using Profile Information to Assist Classic Code Optimizations. [Citation Graph (0, 0)][DBLP]
    Softw., Pract. Exper., 1991, v:21, n:12, pp:1301-1321 [Journal]
  21. Pohua P. Chang, Daniel M. Lavery, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:3, pp:353-370 [Journal]
  22. Pohua P. Chang, Nancy J. Warter, Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu
    Three Architecutral Models for Compiler-Controlled Speculative Execution. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1995, v:44, n:4, pp:481-494 [Journal]
  23. William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu
    The Effect of Code Expanding Optimizations on Instruction Cache Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1993, v:42, n:9, pp:1045-1057 [Journal]
  24. Wen-mei W. Hwu, Pohua P. Chang
    Efficient Instruction Sequencing with Inline Target Insertion. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:12, pp:1537-1551 [Journal]

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