Hiroomi Hikawa Pulse Mode Multilayer Neural Network with Floating Point Operation and On-Chip Learning. [Citation Graph (0, 0)][DBLP] IJCNN (2), 2000, pp:71-80 [Conf]
Hiroomi Hikawa Pulse mode neuron with leakage integrator and additive random noise. [Citation Graph (0, 0)][DBLP] ISCAS (5), 2003, pp:821-824 [Conf]
Hiroomi Hikawa Direct digital frequency synthesizer with multi-stage linear interpolation. [Citation Graph (0, 0)][DBLP] ISCAS (4), 2004, pp:233-236 [Conf]
Hiroomi Hikawa FPGA implementation of self organizing map with digital phase locked loops. [Citation Graph (0, 0)][DBLP] Neural Networks, 2005, v:18, n:5-6, pp:514-522 [Journal]
Hiroomi Hikawa An efficient three-valued multilayer neural network with on-chip learning suitable for hardware implementation. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2000, v:31, n:4, pp:43-51 [Journal]
Hiroomi Hikawa A multilayer neural network with pulse position modulation. [Citation Graph (0, 0)][DBLP] Systems and Computers in Japan, 2003, v:34, n:13, pp:36-46 [Journal]