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Kisaburo Nakazawa: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hiroshi Nakamura, Kisaburo Nakazawa, Hang Li, Hiromitsu Imori, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
    Evaluation of Pseudo Vector Processor Based on Slide-Windowed Registers. [Citation Graph (0, 0)][DBLP]
    HICSS (1), 1994, pp:368-377 [Conf]
  2. Kotaro Shimamura, Shigeya Tanaka, Tetsuya Shimomura, Takashi Hotta, Eiki Kamada, Hideo Sawamoto, Teruhisa Shimizu, Kisaburo Nakazawa
    A superscalar RISC processor with pseudo vector processing feature. [Citation Graph (0, 0)][DBLP]
    ICCD, 1995, pp:102-109 [Conf]
  3. Taisuke Boku, Ken'ichi Itakura, Hiroshi Nakamura, Kisaburo Nakazawa
    CP-PACS: A Massively Parallel Processor for Large Scale Scientific Calculations. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:108-115 [Conf]
  4. Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita
    A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1993, pp:298-307 [Conf]
  5. Kisaburo Nakazawa, Hiroshi Nakamura, Hiromitsu Imori, Shun Kawabe
    Pseudo Vector Processor Based on Register-Windowed Superscalar Pipeline. [Citation Graph (0, 0)][DBLP]
    SC, 1992, pp:642-651 [Conf]
  6. Kisaburo Nakazawa, Hiroshi Nakamura, Taisuke Boku, Ikuo Nakata, Yoshiyuki Yamashita
    CP-PACS: A massively parallel processor at the University of Tsukuba. [Citation Graph (0, 0)][DBLP]
    Parallel Computing, 1999, v:25, n:13-14, pp:1635-1661 [Journal]

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