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Ramesh Illikkal: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Srihari Makineni, Ravishankar R. Iyer, Partha Sarangam, Donald Newell, Li Zhao, Ramesh Illikkal, Jaideep Moses
    Receive Side Coalescing for Accelerating TCP/IP Processing. [Citation Graph (0, 0)][DBLP]
    HiPC, 2006, pp:289-300 [Conf]
  2. Jaideep Moses, Ramesh Illikkal, Ravi R. Iyer, Ram Huggahalli, Donald Newell
    ASPEN: Towards Effective Simulation of Threads and Engines in Evolving Platforms. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2004, pp:51-58 [Conf]
  3. Greg J. Regnier, Srihari Makineni, Ramesh Illikkal, Ravi R. Iyer, Dave B. Minturn, Ram Huggahalli, Donald Newell, Linda S. Cline, Annie Foong
    TCP Onloading for Data Center Servers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:11, pp:48-58 [Journal]
  4. Ravi R. Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt
    QoS policies and architecture for cache/memory in CMP platforms. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:25-36 [Conf]
  5. Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer, Jaideep Moses, Donald Newell, Renato J. O. Figueiredo
    I/O processing in a virtualized platform: a simulation-driven approach. [Citation Graph (0, 0)][DBLP]
    VEE, 2007, pp:116-125 [Conf]
  6. Ravi R. Iyer, Mahesh Bhat, Li Zhao, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell
    Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:191-200 [Conf]
  7. Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell
    Exploring Large-Scale CMP Architectures Using ManySim. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:21-33 [Journal]

  8. CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. [Citation Graph (, )][DBLP]


  9. qTLB: Looking Inside the Look-Aside Buffer. [Citation Graph (, )][DBLP]


  10. HiPPAI: High Performance Portable Accelerator Interface for SoCs. [Citation Graph (, )][DBLP]


  11. Constraint-Aware Large-Scale CMP Cache Design. [Citation Graph (, )][DBLP]


  12. Exploring DRAM cache architectures for CMP server platforms. [Citation Graph (, )][DBLP]


  13. Rate-based QoS techniques for cache/memory in CMP platforms. [Citation Graph (, )][DBLP]


  14. Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. [Citation Graph (, )][DBLP]


  15. CMPSched$im: Evaluating OS/CMP interaction on shared cache management. [Citation Graph (, )][DBLP]


  16. A Simulation Framework for the Analysis of the TLB Behavior in Virtualized Environments. [Citation Graph (, )][DBLP]


  17. TMT - A TLB Tag Management Framework for Virtualized Platforms. [Citation Graph (, )][DBLP]


  18. Hardware/Software Co-Simulation for Last Level Cache Exploration. [Citation Graph (, )][DBLP]


  19. VM3: Measuring, modeling and managing VM shared resources. [Citation Graph (, )][DBLP]


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