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Publications of Author

1. Jung Ho Ahn, Mattan Erez, William J. Dally
   Scatter-Add in Data Parallel Architectures. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:132-142 [Conf]
   
2. Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen
   eXtended Block Cache. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:61-0 [Conf]
   
3. Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
   Stream Register Files with Indexed Access. [Citation Graph (0, 0)][DBLP]
   HPCA, 2004, pp:60-72 [Conf]
   
4. Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan
   Speculation Techniques for Improving Load Related Instruction Scheduling. [Citation Graph (0, 0)][DBLP]
   ISCA, 1999, pp:42-53 [Conf]
   
5. Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
   Compilation for explicitly managed memory hierarchies. [Citation Graph (0, 0)][DBLP]
   PPOPP, 2007, pp:226-236 [Conf]
   
6. William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi
   Merrimac: Supercomputing with Streams. [Citation Graph (0, 0)][DBLP]
   SC, 2003, pp:35- [Conf]
   
7. Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve
   Analysis and Performance Results of a Molecular Modeling Application on Merrimac. [Citation Graph (0, 0)][DBLP]
   SC, 2004, pp:42- [Conf]
   
8. Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
   Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. [Citation Graph (0, 0)][DBLP]
   SC, 2005, pp:29- [Conf]
   
9. Jung Ho Ahn, Mattan Erez, William J. Dally
   Architecture - The design space of data-parallel memory systems. [Citation Graph (0, 0)][DBLP]
   SC, 2006, pp:80- [Conf]
   
10. Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan
    Memory - Sequoia: programming the memory hierarchy. [Citation Graph (0, 0)][DBLP]
    SC, 2006, pp:83- [Conf]
    
11. Jung Ho Ahn, Mattan Erez, William J. Dally
    Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:126-137 [Conf]
    
12. Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally
    Executing irregular scientific applications on stream architectures. [Citation Graph (0, 0)][DBLP]
    ICS, 2007, pp:93-104 [Conf]
    
13. 
    Architectural Support for the Stream Execution Model on General-Purpose Processors. [Citation Graph (, )][DBLP]
    
    
14. 
    Virtualized and flexible ECC for main memory. [Citation Graph (, )][DBLP]
    
    
15. 
    NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. [Citation Graph (, )][DBLP]
    
    
16. 
    Memory mapped ECC: low-cost error protection for last level caches. [Citation Graph (, )][DBLP]
    
    
17. 
    NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime. [Citation Graph (, )][DBLP]
    
    
18. 
    Flexible cache error protection using an ECC FIFO. [Citation Graph (, )][DBLP]
    
    
19. 
    Packet-level static timing analysis for NoCs. [Citation Graph (, )][DBLP]