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Naveen Muralimanohar: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy
    Microarchitectural Wire Management for Performance and Power in Partitioned Architectures. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:28-39 [Conf]
  2. Liqun Cheng, Naveen Muralimanohar, Karthik Ramani, Rajeev Balasubramonian, John B. Carter
    Interconnect-Aware Coherence Protocols for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2006, pp:339-351 [Conf]
  3. Naveen Muralimanohar, Rajeev Balasubramonian
    Interconnect design considerations for large NUCA caches. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:369-380 [Conf]
  4. Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Liqun Cheng, John B. Carter
    Leveraging Wire Properties at the Microarchitecture Level. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:6, pp:40-52 [Journal]

  5. Scalable and reliable communication for hardware transactional memory. [Citation Graph (, )][DBLP]

  6. Non-uniform power access in large caches with low-swing wires. [Citation Graph (, )][DBLP]

  7. Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy. [Citation Graph (, )][DBLP]

  8. Rethinking DRAM design and organization for energy-constrained multi-cores. [Citation Graph (, )][DBLP]

  9. Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. [Citation Graph (, )][DBLP]

  10. Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]

  11. Leveraging 3D PCRAM technologies to reduce checkpoint overhead for future exascale systems. [Citation Graph (, )][DBLP]

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