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Publications of Author

1. Takeo Hosomi, Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose
   A DSM Architecture for a Parallel Computer Cenju-4. [Citation Graph (0, 0)][DBLP]
   HPCA, 2000, pp:287-0 [Conf]
   
2. Tsutomu Maruyama, Tetsuya Hirose, Akihiko Konagaya
   A Fine-Grained Parallel Genetic Algorithm for Distributed Parallel Systems. [Citation Graph (0, 0)][DBLP]
   ICGA, 1993, pp:184-190 [Conf]
   
3. Yasushi Kanoh, Masaaki Nakamura, Tetsuya Hirose, Takeo Hosomi, Hirokazu Takayama, Toshiyuki Nakata
   Message Passing Communication in a Parallel Computer Cenju-4. [Citation Graph (0, 0)][DBLP]
   ISHPC, 1999, pp:55-70 [Conf]
   
4. Masayuki Furuhashi, Tetsuya Hirose, Hiroshi Tsuji, Masayuki Tachi, Kenji Taniguchi
   Atomic configuration of boron pile-up at the Si/SiO2 interface. [Citation Graph (0, 0)][DBLP]
   IEICE Electronic Express, 2004, v:1, n:6, pp:126-130 [Journal]
   
5. Yusuke Kanazawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
   A MOS circuit for bursting neural oscillators with excitable oregonators. [Citation Graph (0, 0)][DBLP]
   IEICE Electronic Express, 2004, v:1, n:4, pp:73-76 [Journal]
   
6. Hiroshi Matsubara, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
   Reaction-diffusion chip implementing excitable lattices with multiple-valued cellular automata. [Citation Graph (0, 0)][DBLP]
   IEICE Electronic Express, 2004, v:1, n:9, pp:248-252 [Journal]
   
7. Sungwoo Cha, Tetsuya Hirose, Masaki Haruoka, Toshimasa Matsuoka, Kenji Taniguchi
   A CMOS IF Variable Gain Amplifier with Exponential Gain Control. [Citation Graph (0, 0)][DBLP]
   IEICE Transactions, 2005, v:88, n:2, pp:410-415 [Journal]
   
8. Tetsuya Asai, Masayuki Ikebe, Tetsuya Hirose, Yoshihito Amemiya
   A quadrilateral-object composer for binary images with reaction-diffusion cellular automata. [Citation Graph (0, 0)][DBLP]
   Parallel Algorithms Appl., 2005, v:20, n:1, pp:57-67 [Journal]
   
9. Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya
   Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. [Citation Graph (0, 0)][DBLP]
   ISCAS, 2007, pp:3748-3751 [Conf]
   
10. Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Hatsuo Hayashi, Yoshihito Amemiya
    A subthreshold CMOS circuit for a piecewise linear neuromorphic oscillator with current-mode low-pass filters. [Citation Graph (0, 0)][DBLP]
    Neurocomputing, 2007, v:71, n:1-3, pp:3-12 [Journal]
    
11. 
    A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. [Citation Graph (, )][DBLP]
    
    
12. 
    Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. [Citation Graph (, )][DBLP]
    
    
13. 
    Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. [Citation Graph (, )][DBLP]