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Ravi R. Iyer: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Ravi R. Iyer, Laxmi N. Bhuyan
    Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    HPCA, 1999, pp:152-160 [Conf]
  2. Srihari Makineni, Ravi R. Iyer
    Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor. [Citation Graph (0, 0)][DBLP]
    HPCA, 2004, pp:152-163 [Conf]
  3. Li Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell
    Hardware Support for Bulk Data Movement in Server Platforms. [Citation Graph (0, 0)][DBLP]
    ICCD, 2005, pp:53-60 [Conf]
  4. Padma Apparao, Ravi R. Iyer, Ricardo Morin, Naren Nayak, Mahesh Bhat, David Halliwell, William Steinberg
    Architectural Characterization of an XML-Centric Commercial Server Workload. [Citation Graph (0, 0)][DBLP]
    ICPP, 2004, pp:292-300 [Conf]
  5. Ravi R. Iyer
    CQoS: a framework for enabling QoS in shared caches of CMP platforms. [Citation Graph (0, 0)][DBLP]
    ICS, 2004, pp:257-266 [Conf]
  6. Ravi R. Iyer, Nancy M. Amato, Lawrence Rauchwerger, Laxmi N. Bhuyan
    Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1999, pp:339-347 [Conf]
  7. Laxmi N. Bhuyan, Hu-Jun Wang, Ravi R. Iyer, Akhilesh Kumar
    Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPPS/SPDP, 1998, pp:466-474 [Conf]
  8. Ravi R. Iyer
    Exploring the Cache Design Space for Web Servers. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2001, pp:67- [Conf]
  9. Ravi R. Iyer, Laxmi N. Bhuyan, Ashwini K. Nanda
    Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2000, pp:721-728 [Conf]
  10. Rong Yu, Laxmi N. Bhuyan, Ravi R. Iyer
    Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2002, pp:- [Conf]
  11. Ram Huggahalli, Ravi R. Iyer, Scott Tetrick
    Direct Cache Access for High Bandwidth Network I/O. [Citation Graph (0, 0)][DBLP]
    ISCA, 2005, pp:50-59 [Conf]
  12. Padma Apparao, Ravi R. Iyer, Donald Newell
    Architectural Characterization of VM Scaling on an SMP Machine. [Citation Graph (0, 0)][DBLP]
    ISPA Workshops, 2006, pp:464-473 [Conf]
  13. Ravi R. Iyer
    On Modeling and Analyzing Cache Hierarchies using CASPER. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2003, pp:182-187 [Conf]
  14. Jaideep Moses, Ramesh Illikkal, Ravi R. Iyer, Ram Huggahalli, Donald Newell
    ASPEN: Towards Effective Simulation of Threads and Engines in Evolving Platforms. [Citation Graph (0, 0)][DBLP]
    MASCOTS, 2004, pp:51-58 [Conf]
  15. Keshavan Varadarajan, S. K. Nandy, Vishal Sharda, Amrutur Bharadwaj, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:433-442 [Conf]
  16. Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer
    SpliceNP: a TCP splicer using a network processor. [Citation Graph (0, 0)][DBLP]
    ANCS, 2005, pp:135-143 [Conf]
  17. Greg J. Regnier, Srihari Makineni, Ramesh Illikkal, Ravi R. Iyer, Dave B. Minturn, Ram Huggahalli, Donald Newell, Linda S. Cline, Annie Foong
    TCP Onloading for Data Center Servers. [Citation Graph (0, 0)][DBLP]
    IEEE Computer, 2004, v:37, n:11, pp:48-58 [Journal]
  18. Ravi R. Iyer, Jack Perdue, Lawrence Rauchwerger, Nancy M. Amato, Laxmi N. Bhuyan
    An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2005, v:33, n:4, pp:307-350 [Journal]
  19. Li Zhao, Yan Luo, Laxmi N. Bhuyan, Ravi R. Iyer
    A Network Processor-Based, Content-Aware Switch. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2006, v:26, n:3, pp:72-84 [Journal]
  20. Ravi R. Iyer, Laxmi N. Bhuyan
    Design and Evaluation of a Switch Cache Architecture for CC-NUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2000, v:49, n:8, pp:779-797 [Journal]
  21. Li Zhao, Laxmi N. Bhuyan, Ravi R. Iyer, Srihari Makineni, Donald Newell
    Hardware Support for Accelerating Data Movement in Server Platform. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2007, v:56, n:6, pp:740-753 [Journal]
  22. Laxmi N. Bhuyan, Ravi R. Iyer, Tahsin Askar, Ashwini K. Nanda, Mohan Kumar
    Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 1997, v:8, n:1, pp:82-95 [Journal]
  23. Laxmi N. Bhuyan, Ravi R. Iyer, Hu-Jun Wang, Akhilesh Kumar
    Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2000, v:11, n:3, pp:230-246 [Journal]
  24. Ravi R. Iyer
    Characterization and Evaluation of Cache Hierarchies for Web Servers. [Citation Graph (0, 0)][DBLP]
    World Wide Web, 2004, v:7, n:3, pp:259-280 [Journal]
  25. Ravi R. Iyer, Li Zhao, Fei Guo, Ramesh Illikkal, Srihari Makineni, Donald Newell, Yan Solihin, Lisa R. Hsu, Steven K. Reinhardt
    QoS policies and architecture for cache/memory in CMP platforms. [Citation Graph (0, 0)][DBLP]
    SIGMETRICS, 2007, pp:25-36 [Conf]
  26. Vineet Chadha, Ramesh Illikkal, Ravi R. Iyer, Jaideep Moses, Donald Newell, Renato J. O. Figueiredo
    I/O processing in a virtualized platform: a simulation-driven approach. [Citation Graph (0, 0)][DBLP]
    VEE, 2007, pp:116-125 [Conf]
  27. Ravi R. Iyer, Mahesh Bhat, Li Zhao, Ramesh Illikkal, Srihari Makineni, Michael Jones, Kumar Shiv, Donald Newell
    Exploring Small-Scale and Large-Scale CMP Architectures for Commercial Java Servers. [Citation Graph (0, 0)][DBLP]
    IISWC, 2006, pp:191-200 [Conf]
  28. Li Zhao, Ravi R. Iyer, Jaideep Moses, Ramesh Illikkal, Srihari Makineni, Donald Newell
    Exploring Large-Scale CMP Architectures Using ManySim. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:4, pp:21-33 [Journal]

  29. CacheScouts: Fine-Grain Monitoring of Shared Caches in CMP Platforms. [Citation Graph (, )][DBLP]


  30. qTLB: Looking Inside the Look-Aside Buffer. [Citation Graph (, )][DBLP]


  31. Constraint-Aware Large-Scale CMP Cache Design. [Citation Graph (, )][DBLP]


  32. Achieving 10Gbps Network Processing: Are We There Yet?. [Citation Graph (, )][DBLP]


  33. Exploring DRAM cache architectures for CMP server platforms. [Citation Graph (, )][DBLP]


  34. Rate-based QoS techniques for cache/memory in CMP platforms. [Citation Graph (, )][DBLP]


  35. Anatomy and Performance of SSL Processing. [Citation Graph (, )][DBLP]


  36. Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. [Citation Graph (, )][DBLP]


  37. Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. [Citation Graph (, )][DBLP]


  38. CMPSched$im: Evaluating OS/CMP interaction on shared cache management. [Citation Graph (, )][DBLP]


  39. Characterization & analysis of a server consolidation benchmark. [Citation Graph (, )][DBLP]


  40. Implications of cache asymmetry on server consolidation performance. [Citation Graph (, )][DBLP]


  41. Hardware/Software Co-Simulation for Last Level Cache Exploration. [Citation Graph (, )][DBLP]


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