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Chris Wilkerson: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. [Citation Graph (0, 0)][DBLP]
    HPCA, 2003, pp:129-140 [Conf]
  2. Srikanth T. Srinivasan, Roy Dz-Ching Ju, Alvin R. Lebeck, Chris Wilkerson
    Locality vs. criticality. [Citation Graph (0, 0)][DBLP]
    ISCA, 2001, pp:132-143 [Conf]
  3. Renju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark
    Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History. [Citation Graph (0, 0)][DBLP]
    ISCA, 2003, pp:314-323 [Conf]
  4. Edward Brekelbaum, Jeff Rupley, Chris Wilkerson, Bryan Black
    Hierarchical Scheduling Windows. [Citation Graph (0, 0)][DBLP]
    MICRO, 2002, pp:27-36 [Conf]
  5. Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson
    Parallel depth first vs. work stealing schedulers on CMP architectures. [Citation Graph (0, 0)][DBLP]
    SPAA, 2006, pp:330- [Conf]
  6. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
    Runahead Execution: An Effective Alternative to Large Instruction Windows. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2003, v:23, n:6, pp:20-25 [Journal]
  7. Shimin Chen, Phillip B. Gibbons, Michael Kozuch, Vasileios Liaskovitis, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Todd C. Mowry, Chris Wilkerson
    Scheduling threads for constructive cache sharing on CMPs. [Citation Graph (0, 0)][DBLP]
    SPAA, 2007, pp:105-115 [Conf]

  8. Circuit techniques for dynamic variation tolerance. [Citation Graph (, )][DBLP]


  9. Resilient circuits - Enabling energy-efficient performance and reliability. [Citation Graph (, )][DBLP]


  10. Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. [Citation Graph (, )][DBLP]


  11. Reducing cache power with low-cost, multi-bit error-correcting codes. [Citation Graph (, )][DBLP]


  12. Impact of die-to-die and within-die parameter variations on the throughput distribution of multi-core processors. [Citation Graph (, )][DBLP]


  13. Resilient microprocessor design for high performance & energy efficiency. [Citation Graph (, )][DBLP]


  14. Low power adaptive pipeline based on instruction isolation. [Citation Graph (, )][DBLP]


  15. Improving cache lifetime reliability at ultra-low voltages. [Citation Graph (, )][DBLP]


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