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Nevin Kirman: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
    Checkpointed Early Load Retirement. [Citation Graph (0, 0)][DBLP]
    HPCA, 2005, pp:16-27 [Conf]
  2. Meyrem Kirman, Nevin Kirman, José F. Martínez
    Cherry-MP: Correctly Integrating Checkpointed Early Resource Recycling in Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2005, pp:245-256 [Conf]
  3. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    Leveraging Optical Technology in Future Bus-based Chip Multiprocessors. [Citation Graph (0, 0)][DBLP]
    MICRO, 2006, pp:492-503 [Conf]
  4. Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez
    A Reconfigurable Chip Multiprocessor Architecture to Accommodate Software Diversity. [Citation Graph (0, 0)][DBLP]
    IPDPS, 2007, pp:1-6 [Conf]
  5. Engin Ipek, Meyrem Kirman, Nevin Kirman, José F. Martínez
    Core fusion: accommodating software diversity in chip multiprocessors. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:186-197 [Conf]
  6. Nevin Kirman, Meyrem Kirman, Rajeev K. Dokania, José F. Martínez, Alyssa B. Apsel, Matthew A. Watkins, David H. Albonesi
    On-Chip Optical Technology in Future Bus-Based Multicore Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Micro, 2007, v:27, n:1, pp:56-66 [Journal]

  7. A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing. [Citation Graph (, )][DBLP]


  8. Scavenger: A New Last Level Cache Architecture with Global Block Priority. [Citation Graph (, )][DBLP]


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