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Publications of Author

1. Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez
   Checkpointed Early Load Retirement. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:16-27 [Conf]
   
2. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich
   Leveraging cache coherence in active memory systems. [Citation Graph (0, 0)][DBLP]
   ICS, 2002, pp:2-13 [Conf]
   
3. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich
   Active Memory Techniques for ccNUMA Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IPDPS, 2003, pp:10- [Conf]
   
4. Mainak Chaudhuri, Mark Heinrich
   SMTp: An Architecture for Next-generation Scalable Multi-threading. [Citation Graph (0, 0)][DBLP]
   ISCA, 2004, pp:124-137 [Conf]
   
5. Mark Heinrich, Evan Speight, Mainak Chaudhuri
   Active Memory Clusters: Efficient Multiprocessing on Commodity Clusters. [Citation Graph (0, 0)][DBLP]
   ISHPC, 2002, pp:78-92 [Conf]
   
6. Mainak Chaudhuri, Daehyun Kim, Mark Heinrich
   Cache Coherence Protocol Design for Active Memory Systems. [Citation Graph (0, 0)][DBLP]
   PDPTA, 2002, pp:83-89 [Conf]
   
7. Mark Heinrich, Mainak Chaudhuri
   Ocean warning: avoid drowning. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:3, pp:30-32 [Journal]
   
8. Mainak Chaudhuri, Mark Heinrich, Chris Holt, Jaswinder Pal Singh, Edward Rothberg, John L. Hennessy
   Latency, Occupancy, and Bandwidth in DSM Multiprocessors: A Performance Evaluation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2003, v:52, n:7, pp:862-880 [Journal]
   
9. Daehyun Kim, Mainak Chaudhuri, Mark Heinrich, Evan Speight
   Architectural Support for Uniprocessor and Multiprocessor Active Memory Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:3, pp:288-307 [Journal]
   
10. Mainak Chaudhuri, Mark Heinrich
    The Impact of Negative Acknowledgments in Shared Memory Scientific Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:2, pp:134-150 [Journal]
    
11. Mainak Chaudhuri, Mark Heinrich
    Exploring Virtual Network Selection Algorithms in DSM Cache Coherence Protocols. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2004, v:15, n:8, pp:699-712 [Journal]
    
12. Lakshmana Rao Vittanala, Mainak Chaudhuri
    Integrating Memory Compression and Decompression with Coherence Protocols in Distributed Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    ICPP, 2007, pp:4- [Conf]
    
13. Mainak Chaudhuri, Mark Heinrich
    Integrated Memory Controllers with Parallel Coherence Streams. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Parallel Distrib. Syst., 2007, v:18, n:8, pp:1159-1173 [Journal]
    
14. 
    PageNUCA: Selected policies for page-grain locality management in large shared chip-multiprocessor caches. [Citation Graph (, )][DBLP]
    
    
15. 
    LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation. [Citation Graph (, )][DBLP]
    
    
16. 
    Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. [Citation Graph (, )][DBLP]
    
    
17. 
    Scavenger: A New Last Level Cache Architecture with Global Block Priority. [Citation Graph (, )][DBLP]
    
    
18. 
    Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. [Citation Graph (, )][DBLP]