Search the dblp DataBase

Publications of Author

1. Zhichun Zhu, Zhao Zhang
   A Performance Comparison of DRAM Memory System Optimizations for SMT Processors. [Citation Graph (0, 0)][DBLP]
   HPCA, 2005, pp:213-224 [Conf]
   
2. Zhichun Zhu, Zhao Zhang, Xiaodong Zhang
   Fine-Grain Priority Scheduling on Multi-Channel Memory Systems. [Citation Graph (0, 0)][DBLP]
   HPCA, 2002, pp:107-116 [Conf]
   
3. Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
   A permutation-based page interleaving scheme to reduce row-buffer conflicts and exploit data locality. [Citation Graph (0, 0)][DBLP]
   MICRO, 2000, pp:32-41 [Conf]
   
4. Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
   Breaking Address Mapping Symmetry at Multi-levels of Memory Heirarchy to Reduce DRAM Row-buffer Conflicts. [Citation Graph (0, 0)][DBLP]
   J. Instruction-Level Parallelism, 2001, v:3, n:, pp:- [Journal]
   
5. Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
   Cached DRAM for ILP Processor Memory Access Latency Reduction. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2001, v:21, n:4, pp:22-32 [Journal]
   
6. Zhichun Zhu, Xiaodong Zhang
   Access-Mode Predictions for Low-Power Cache Design. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2002, v:22, n:2, pp:58-71 [Journal]
   
7. Zhichun Zhu, Xiaodong Zhang
   Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. [Citation Graph (0, 0)][DBLP]
   IEEE Micro, 2005, v:25, n:4, pp:10-19 [Journal]
   
8. Xing Du, Xiaodong Zhang, Zhichun Zhu
   Memory Hierarchy Considerations for Cost-Effective Cluster Computing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2000, v:49, n:9, pp:915-933 [Journal]
   
9. Zhao Zhang, Zhichun Zhu, Xiaodong Zhang
   Design and Optimization of Large Size and Low Overhead Off-Chip Caches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:7, pp:843-855 [Journal]
   
10. Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Howard David, Zhao Zhang
    Thermal modeling and management of DRAM memory systems. [Citation Graph (0, 0)][DBLP]
    ISCA, 2007, pp:312-322 [Conf]
    
11. 
    Memory Access Scheduling Schemes for Systems with Multi-Core Processors. [Citation Graph (, )][DBLP]
    
    
12. 
    Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. [Citation Graph (, )][DBLP]
    
    
13. 
    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. [Citation Graph (, )][DBLP]
    
    
14. 
    Mini-rank: Adaptive DRAM architecture for improving memory power efficiency. [Citation Graph (, )][DBLP]
    
    
15. 
    Software thermal management of dram memory for multicore systems. [Citation Graph (, )][DBLP]