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Hironori Nakajo: [Publications] [Author Rank by year] [Co-authors] [Prefers] [Cites] [Cited by]

Publications of Author

  1. Hironori Nakajo, Hidekazu Tanaka, Yoshinori Nakanishi, Masaki Kohata, Yukio Kaneda
    Distributed Shared-Memory for a Workstation Cluster with a High Speed Serial Interface. [Citation Graph (0, 0)][DBLP]
    HPCN Europe, 1998, pp:588-597 [Conf]
  2. Hironori Nakajo, Satoshi Ohtani, Yukio Kaneda
    A Simulation-based Evaluation of a Disk I/O Subsystem for a Massively Parallel Computer: JUMP-1. [Citation Graph (0, 0)][DBLP]
    ICDCS, 1996, pp:562-569 [Conf]
  3. Hironori Nakajo, Satoshi Ohtani, Takashi Matsumoto, Masadi Kohata, Kei Hiraki, Yukio Kaneda
    An I/O Network Architecture of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. [Citation Graph (0, 0)][DBLP]
    International Conference on Supercomputing, 1997, pp:253-260 [Conf]
  4. Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
    An Implementation and Evaluation of a Distributed Shared-Memory System on Workstation Clusters Using Fast Serial Links. [Citation Graph (0, 0)][DBLP]
    ISHPC, 1997, pp:143-158 [Conf]
  5. Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
    On-the-fly Sending: A Low Latency High Bandwidth Message Transfer Mechanism. [Citation Graph (0, 0)][DBLP]
    ISPAN, 2000, pp:186-194 [Conf]
  6. Noboru Tanabe, Yoshihiro Hamada, Hironori Nakajo, Hideki Imashiro, Junji Yamamoto, Tomohiro Kudoh, Hideharu Amano
    Low Latency Communication on DIMMnet-1 Network Interface Plugged into a DIMM Slot. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2002, pp:9-14 [Conf]
  7. Noboru Tanabe, Hironori Nakajo, Hirotaka Hakozaki, Masasige Nakatake, Yasunori Dohi, Hideharu Amano
    A New Memory Module for Memory Intensive Applications. [Citation Graph (0, 0)][DBLP]
    PARELEC, 2004, pp:123-128 [Conf]
  8. Akira Kitamura, Yasuo Miyabe, Tetsu Izawa, Tomotaka Miyashiro, Konosuke Watanabe, Tomohiro Otsuka, Hideharu Amano, Yoshihiro Hamada, Noboru Tanabe, Hironori Nakajo
    Evaluation of Network Interface Controller on DIMMnet-2 Prototype Board. [Citation Graph (0, 0)][DBLP]
    PDCAT, 2005, pp:778-780 [Conf]
  9. Hironori Nakajo, Takashi Matsumoto, Masaki Kohata, Hideo Matsuda, Kei Hiraki, Yukio Kaneda
    High Performance I/O System of the Distributed Shared-Memory Massively Parallel Computer JUMP-1. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Systems, 1995, pp:470-473 [Conf]
  10. Yoshihiro Hamada, Hiroaki Nishi, Akira Kitamura, Noboru Tanabe, Hideharu Amano, Hironori Nakajo
    A Packet Forwarding Layer for DIMMnet and its Hardware Implementation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:461-467 [Conf]
  11. Jun Kanai, Takuro Mori, Takeshi Araki, Noboru Tanabe, Hironori Nakajo, Mitaro Namiki
    Implementation of PC Cluster System with Memory Mapped File by Commodity OS. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:902-908 [Conf]
  12. Norito Kato, Masanori Yamato, Osamu Tujimoto, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
    Dynamic Allocation of Physical Register Banks for an SMT Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2004, pp:317-323 [Conf]
  13. Hironori Nakajo, M. Ishii, T. Kudo, Hideharu Amano
    Coherence Protocol for Home Proxy Cache on RHiNET. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2000, pp:- [Conf]
  14. Hironori Nakajo, Masanori Yamato, Shoji Kawahara, Norito Kato, Koichi Sasada, Mikiko Sato, Mitaro Namiki
    Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1775-1781 [Conf]
  15. Yoshiyasu Ogasawara, Norito Kato, Masanori Yamato, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Mitaro Namiki, Hironori Nakajo
    A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:447-453 [Conf]
  16. Yoshiyasu Ogasawara, Ippei Tate, Satoshi Watanabe, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Mitaro Namiki, Hironori Nakajo
    Towards Reconfigurable Cache Memory for a Multithreaded Processor. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:916-924 [Conf]
  17. Koichi Sasada, Mikiko Sato, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
    Implementation and Evaluation of a Thread Library for Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:609-615 [Conf]
  18. Mikiko Sato, Koichi Sasada, Shoji Kawahara, Norito Kato, Masanori Yamato, Hironori Nakajo, Mitaro Namiki
    A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2003, pp:1669-1675 [Conf]
  19. Ippei Tate, Yoshiyasu Ogasawara, Mikiko Sato, Koichi Sasada, Kaname Uchikura, Kazunari Asano, Satoshi Watanabe, Mitaro Namiki, Hironori Nakajo
    A Model of Implementable SMT Processor on FPGA. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2006, pp:909-915 [Conf]
  20. Kaname Uchikura, Koichi Sasada, Mikiko Sato, Masanori Yamato, Norito Kato, Hironori Nakajo, Mitaro Namiki
    Development of a Thread Scheduler for SMT Processor Architecture. [Citation Graph (0, 0)][DBLP]
    PDPTA, 2005, pp:454-460 [Conf]
  21. Noboru Tanabe, Junji Yamamoto, Hiroaki Nishi, Tomohiro Kudoh, Yoshihiro Hamada, Hironori Nakajo, Hideharu Amano
    Low Latency High Bandwidth Message Transfer Mechanisms for a Network Interface Plugged into a Memory Slot. [Citation Graph (0, 0)][DBLP]
    Cluster Computing, 2002, v:5, n:1, pp:7-17 [Journal]
  22. Hironori Nakajo, Akihiro Ichikawa, Yukio Kaneda
    A Distributed Shared-Memory System on a Workstation Cluster Using Fast Serial Links. [Citation Graph (0, 0)][DBLP]
    International Journal of Parallel Programming, 2000, v:28, n:2, pp:179-194 [Journal]
  23. Tomotaka Miyashiro, Akira Kitamura, Hironori Nakajo, Noboru Tanabe
    DIMMnet-2: A Reconfigurable Board Connected Into a Memory Slot. [Citation Graph (0, 0)][DBLP]
    FPL, 2006, pp:1-4 [Conf]
  24. Akira Kitamura, Yasuo Miyabe, Tomotaka Miyashiro, Noboru Tanabe, Hironori Nakajo, Hideharu Amano
    Performance evaluation on low-latency communication mechanism of DIMMnet-2. [Citation Graph (0, 0)][DBLP]
    Parallel and Distributed Computing and Networks, 2007, pp:57-62 [Conf]

  25. Low-Complexity Bypass Network Using Small RAM. [Citation Graph (, )][DBLP]


  26. Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor. [Citation Graph (, )][DBLP]


  27. MEMOnet : Network interface plugged into a memory slot. [Citation Graph (, )][DBLP]


  28. An Effective Replacement Strategy of Cache Memory for an SMT Processor. [Citation Graph (, )][DBLP]


  29. An Enhancer of Memory and Network for Cluster and its Applications. [Citation Graph (, )][DBLP]


  30. Implementation and Evaluation of Multicast Mechanism on Network Interface Plugged into a Memory Slot. [Citation Graph (, )][DBLP]


  31. Toward Parallel and Distributed Processing on High-Density Network with Mobile Devices. [Citation Graph (, )][DBLP]


  32. The architecture of visualization system using memory with memory-side gathering and CPUs with DMA-type memory accessing. [Citation Graph (, )][DBLP]


  33. Introduction to Acceleration for MPI Derived Datatypes Using an Enhancer of Memory and Network. [Citation Graph (, )][DBLP]


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