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Publications of Author

1. Xuehong Sun, Sartaj K. Sahni, Yiqiang Q. Zhao
   Fast Update Algorithm for IP Forwarding Table Using Independent Sets. [Citation Graph (0, 0)][DBLP]
   HSNMC, 2004, pp:324-335 [Conf]
   
2. Mario A. Lopez, Ravi Janardan, Sartaj K. Sahni
   A fast algorithm for VLSI net extraction. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1993, pp:770-774 [Conf]
   
3. Venkat Thanvantri, Sartaj K. Sahni
   Folding a stack of equal width components. [Citation Graph (0, 0)][DBLP]
   ICCAD, 1994, pp:432-435 [Conf]
   
4. Haibin Lu, Sartaj K. Sahni
   A B-tree dynamic router-table design. [Citation Graph (0, 0)][DBLP]
   ISCC, 2004, pp:840-845 [Conf]
   
5. Haibin Lu, Sartaj K. Sahni
   Dynamic IP router-tables using highest-priority matching. [Citation Graph (0, 0)][DBLP]
   ISCC, 2004, pp:858-863 [Conf]
   
6. Andrew Lim, Sartaj K. Sahni, Venkat Thanvantri
   A fast algorithm to test planar topological routability. [Citation Graph (0, 0)][DBLP]
   VLSI Design, 1995, pp:8-12 [Conf]
   
7. Dinesh P. Mehta, Sartaj K. Sahni
   Models, techniques, and algorithms for finding, selecting, and displaying patterns in strings and other discrete objects. [Citation Graph (0, 0)][DBLP]
   Journal of Systems and Software, 1997, v:39, n:3, pp:201-221 [Journal]
   
8. Haibin Lu, Kun Suk Kim, Sartaj K. Sahni
   Prefix and Interval-Partitioned Dynamic IP Router-Tables. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:5, pp:545-557 [Journal]
   
9. Sangyong Han, Sartaj K. Sahni
   Layering Algorithms For Single-Row Routing. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:95-102 [Journal]
   
10. Rajiv Kane, Sartaj K. Sahni
    A Systolic Design-Rule Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1987, v:6, n:1, pp:22-32 [Journal]
    
11. Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni
    On path selection in combinational logic circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1989, v:8, n:1, pp:56-63 [Journal]
    
12. Mario A. Lopez, Ravi Janardan, Sartaj K. Sahni
    Efficient net extraction for restricted orientation designs [VLSI layout]. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1996, v:15, n:9, pp:1151-1159 [Journal]
    
13. Surendra Nahar, Sartaj K. Sahni
    Fast algorithm for polygon decomposition. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:473-483 [Journal]
    
14. Sartaj K. Sahni, San-Yuan Wu
    Two NP-hard interchangeable terminal problems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. on CAD of Integrated Circuits and Systems, 1988, v:7, n:4, pp:467-472 [Journal]
    
15. Xuehong Sun, Sartaj K. Sahni, Yiqiang Q. Zhao
    Packet classification consuming small amount of memory. [Citation Graph (0, 0)][DBLP]
    IEEE/ACM Trans. Netw., 2005, v:13, n:5, pp:1135-1145 [Journal]